# HW2 - the figure below when the transistors are in their...

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EE 3193 Intro. to VLSI Homework Assignment 2 Due beginning of class Feb. 15 1. (Problem 2.1 in text) Consider an nMOS transistor in a 0.6 m process with W/L = 4/2 º (i.e., 1.2/0.6 m) . In this process, the gate oxide thickness is 100 ¯ and the mobility of electrons is 350 cm 2 /Vs. The threshold voltage is 0.7 V. Plot I ds for V gs = 0, 1, 2, 3, 4, and 5 V. 2. (Problem 2.2 in text) Show that the current through two transistors in series is equal to the current through a single transistor of twice the length if the transistors are well described by the Shockley model. Specifically show that I DS1 = I DS2 in
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Unformatted text preview: the figure below when the transistors are in their linear regions: V DS < V DD & V t , V DD > V t (this is also true in saturation). Hint: Express the currents of the series transistors in terms of V 1 and solve for V 1 . 3. (Problem 2.14 in text) Peter Pitfall is offering to license to you his patented noninverting buffer circuit shown below. Graphically derive the transfer characteristics for this buffer. Assume n = p = and V tn = | V tp | = V t . Why is it a bad circuit idea? 4. (Problem 4.4 in text) Find the worst case Elmore parasitic delay for an n-input NOR gate....
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## This note was uploaded on 02/02/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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