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Unformatted text preview: the figure below when the transistors are in their linear regions: V DS < V DD & V t , V DD > V t (this is also true in saturation). Hint: Express the currents of the series transistors in terms of V 1 and solve for V 1 . 3. (Problem 2.14 in text) Peter Pitfall is offering to license to you his patented noninverting buffer circuit shown below. Graphically derive the transfer characteristics for this buffer. Assume n = p = and V tn =  V tp  = V t . Why is it a bad circuit idea? 4. (Problem 4.4 in text) Find the worst case Elmore parasitic delay for an ninput NOR gate....
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This note was uploaded on 02/02/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.
 Spring '10
 HalenLee
 Gate, Transistor

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