HW3 - NOR gate A input. By what percentage do they differ...

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EE 3193 Intro. to VLSI Homework Assignment 3 Due beginning of class March 6 1. (Problem 4.1 in text) Sketch a 2-input NOR gate with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter. Compute the rising and falling propagation delays of the NOR gate driving h identical NOR gates using the Elmore delay model. Assume that every source or drain has fully contacted diffusion when making your estimate of capacitance. . 2. (Problem 4.6 in text) Let a 4x inverter have transistors four times as wide as those of a unit inverter. If a unit inverter has three units of input capacitance and parasitic delay of p inv , what is the input capacitance of a 4x inverter? What is the logical effort? What is the parasitic delay? 3. (Problem 4.16 in text) Find the parasitic delay and logical effort of the X2 and X4
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Unformatted text preview: NOR gate A input. By what percentage do they differ from that of the X1 gate? What does this imply about our model that parasitic delay and logical effort depend only on gate type and not on transistor sizes? 4. (Problem 4.10 in text) Consider the two designs of a 2-input AND gate shown below. Give an intuitive argument about which will be faster. Back up your argument with a calculation of the path effort, delay, and input capacitances x and y to achieve this delay. 5. (Problem 4.24 in text) An output pad contains a chain of successively larger inverters to drive the (relatively) enormous off-chip capacitance. If the first inverter in the chain has an input capacitance of 20 fF and the off-chip load is 10 pF, how many inverters should be used to drive the load with least delay? Estimate this delay, expressed in FO4 inverter delays....
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This note was uploaded on 02/02/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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