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Unformatted text preview: Q delay of the flipflop in terms of the latch timing parameters and t nonoverlap . 4. (Problem 7.9 in text) For the path in the figure below, determine which latches borrow time and if any setup time violations occur. Repeat for cycle times of 1200, 1000, and 800 ps. Assume there is zero clock skew and that the latch delays are accounted for in the propagation delay &amp; s. a. 1 = 550 ps; 2 = 580 ps; 3 = 450 ps; 4 = 200 ps b. 1 = 300 ps; 2 = 600 ps; 3 = 400 ps; 4 = 550 ps 5. (Problem 10.1 in text) Design an 8bit adder. The inputs may drive no more than 30 of transistor width and the output must drive a 20/10 inverter....
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This note was uploaded on 02/02/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.
 Spring '10
 HalenLee
 Gate, Transistor

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