eprom64kbit

eprom64kbit - FINAL Am27C64 64 Kilobit (8 K x 8-Bit) CMOS...

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FINAL Publication# 11419 Rev: E Amendment/ 0 Issue Date: May 1998 Am27C64 64 Kilobit (8 K x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS Fast access time — Speed options as fast as 45 ns Low power consumption — 20 μA typical CMOS standby current JEDEC-approved pinout Single +5 V power supply ± 10% power supply tolerance standard 100% Flashrite™ programming — Typical programming time of 1 second Latch-up protected to 100 mA from –1 V to V CC + 1 V High noise immunity Versatile features for simple interfacing — Both CMOS and TTL input/output compatibility — Two line control functions Standard 28-pin DIP, PDIP, and 32-pin PLCC packages GENERAL DESCRIPTION The Am27C64 is a 64-Kbit, ultraviolet erasable pro- grammable read-only memory. It is organized as 8K words by 8 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic DIP packages, as well as plastic one time programmable (OTP) PDIP and PLCC packages. Data can be typically accessed in less than 45 ns, al- lowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus micro- processor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 80 mW in active mode, and 100 μW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 μs pulses), re- sulting in a typical programming time of 1 second. BLOCK DIAGRAM 11419E-1 A0–A12 Address Inputs PGM# CE# OE# V CC V SS V PP Data Outputs DQ0–DQ7 Output Buffers Y Gating 65,538 Bit Cell Matrix X Decoder Y Decoder Output Enable Chip Enable and Prog Logic
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2 Am27C64 PRODUCT SELECTOR GUIDE CONNECTION DIAGRAMS Top View DIP PLCC Notes: 1. JEDEC nomenclature is in parenthesis. 2.Don’t use (DU) for PLCC. PIN DESIGNATIONS A0–A12 = Address Inputs CE# (E#) = Chip Enable Input DQ0–DQ7 = Data Input/Outputs OE# (G#) = Output Enable Input PGM# (P#) = Program Enable Input V CC =V CC Supply Voltage V PP = Program Voltage Input V SS = Ground NC = No Internal Connection LOGIC SYMBOL Family Part Number Am27C64 Speed Options V CC = 5.0 V ± 5% -255 V CC = 5.0 V ± 10% -45 -55 -70 -90 -120 -150 -200 Max Access Time (ns) 45 55 70 90 120 150 200 250 CE# (E#) Access (ns) 45 55 70 90 120 150 200 250 OE# (G#) Access (ns) 30 35 40 40 50 50 50 50 3 4 5 2 1 9 10 11 12 13 23 22 21 20 19 7 8 18 17 6 28 27 16 14 26 25 24 15 A6 A5 A4 A3 A2 A1 A0 DQ0 A7 DQ1 DQ2 V SS A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7 V CC PGM# (P#) DQ6 NC DQ5 DQ4 DQ3 V PP A12 11419E-2 DQ5 DU DQ4 DQ3 13 1 3 0 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 32 A6 A5 A4 A3 A2 A1 A0 NC DQ0 A8 A9 A11 NC OE# (G#) A10 CE# (E#) DQ7 DQ6 A7 A12 V PP CC PGM# (P#) NC DQ1 DQ2 SS 11419E-3 13 8 DQ0–DQ7 A0–A12 CE# (E#) PMG# (P#) OE# (G#) 11419E-4
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Am27C64 3 ORDERING INFORMATION UV EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
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This note was uploaded on 02/02/2011 for the course CS 2204 taught by Professor Hadimioglu during the Spring '10 term at NYU Poly.

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eprom64kbit - FINAL Am27C64 64 Kilobit (8 K x 8-Bit) CMOS...

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