hw4 - CS 2204 DIGITAL LOGIC STATE MACHINE DESIGN HOMEWORK...

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HOMEWORK IV CS 2204 DIGITAL LOGIC & STATE MACHINE DESIGN FALL 2009 Polytechnic Institute of NYU Page 1 of 14 Handout No : 13 October 22 , 200 9 DUE : November 5, 2009 READ : Related portions of Chapters III, VII and VIII ASSIGNMENT : There are five questions, two of which are developed from Chapter III and VIII of the textbook. Solve all homework and exam problems as shown in class and past exam solutions. 1) Design a modulo-60 (divide-by-60) synchronous up counter circuit by using 4-bit counters studied in class and a few gates : Note that the 4-bit counter studied in class has the following black box view and operation table : z5 z4 z3 z2 C clock msb z1 z0 The count range is 0 through 59. Clearly show the connections of inputs and outputs of the chips and gates. Label all the chip pins. Show what is connected to all inputs and outputs. Modulo-60 Counter 4-bit Up/Down Counter Operation Table LD U/D CE C Operation 0 x 0 Store (DCBA) (Next count is DCBA) 1 0 0 Count Down (Next count is 1 down) 1 1 0 Count Up (Next count is 1 up) x x 1 x Not stored (Do not count up) CE U/D C clock Q2 Q1 Q0 4-bit Up/Down Counter Q3 LD x x x 0 Not stored (Do not count up) A B C D msb msb
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Polytechnic Institute of NYU Page 2 of 14 CS2204 Handout No : 13 October 22 , 200 9 2) Consider the following circuit whose black box view and internal circuitry are given : What is the counting sequence of the above circuit ? That is, determine the purpose of a sequen- tial circuit, i.e. what the circuit does. We do not have to step through the six analysis steps since we know the sequential circuit is a counter with four flip-flops, wiring and gating. All we have to do is the timing analysis and the specification of the purpose : just the 6 th step ! To do the timing analysis, we will start with an arbitrary count on the 4-bit counter, such as, Q3,Q2,Q1,Q0 at 0 , 1 , 0 , 1 , respectively. Then observe the inputs and outputs of the counter until we figure out a pattern which then leads us to the purpose of the sequential circuit. For that, we work on a table that starts with initial input and output values, the values at t0 : Then, get the outputs at t1 from the input values at t0 : a b c d Q2 Q3 0 Q3 d b c clock a Q1 Load Load msb CE U/D C clock Q2 Q1 Q0 4-bit Up/Down Counter Q3 LD A B C D msb msb Q3 Q0 Q3 Q3 U/D LD D C B A Q3 Q2 Q1 Q0 Load Q3 d c b a 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 Q3 => Load Q3 Q2 Q1 Q0 t0 time Q3 is connected to U/D , so at time t0 the U/D value is 0 Initial values U/D LD D C B A Q3 Q2 Q1 Q0 Load Q3 d c b a 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 Q3 Load Q3 Q2 Q1 Q0 t0 time t1 0 1 0 0 1 1 0 1 0 0
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Polytechnic Institute of NYU Page 3 of 14 CS2204 Handout No : 13 October 22 , 200 9 Then, get the input values at t1 from the output values at t1 : Then, get the output values at t2, from the input values at t1 : Continue in this fashion to complete the table.
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This note was uploaded on 02/02/2011 for the course CS 2204 taught by Professor Hadimioglu during the Spring '10 term at NYU Poly.

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hw4 - CS 2204 DIGITAL LOGIC STATE MACHINE DESIGN HOMEWORK...

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