hw6 - CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN HOMEWORK...

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HOMEWORK VI CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN FALL 2009 Polytechnic Institute of NYU Page 1 of 40 Handout No : 19 November 19, 2009 DUE : December 8, 2009 READ : Related portions of Chapters IV, VI, VII, VIII and IX ASSIGNMENT : There are nine questions. Solve all homework and exam problems as shown in class and past exam solutions. 1) Solve Problem 4.14 (d). Draw by hand the corresponding 2-level AND-OR gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB . That is, which TTL LS SSI chips are used, the number of chips used for each kind and the number of unused SSI gates for this 2-level AND-OR gate network. You will point out the distinguished 1-cell(s). Do that by giving their minterm numbers as done in class. Remember also to state whether a term is an essential prime implicant or a secondary essential prime implicant or a prime implicant . 2) By using the minterm list in Problem 4.14 (d), obtain the minimal product-of-sums expres- sion. Draw by hand the corresponding 2-level OR-AND gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB . You will point out the distinguished 0-cell(s). Do that by giving their maxterm numbers . Remember also to state whether a term is an essential prime implicant or a secondary essential prime implicant or a prime implicant . 3) Solve Problem 4.18 (d). Draw by hand the minimal 2-level NAND-NAND gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB . You will not use the method given in Section 4.3.6 in the textbook. You will point out the distinguished 1-cell(s). Do that by giving their minterm numbers . Note that all the don’t cares need not be covered. Remember also to state whether a term is an essen- tial prime implicant or a secondary essential prime implicant or a prime implicant .
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Polytechnic Institute of NYU Page 2 of 40 CS2204 Handout No : 19 November 19, 2009 4) Consider the following minimal SOP expression : f(a, b, c, d) = bd + b d i) Draw the corresponding 2-level AND-OR gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB . That is, which TTL LS SSI chips are used, the number of chips used for each kind and the number of unused SSI gates. ii) Draw the corresponding 2-level NAND-NAND gate network, assuming that single-rail inputs are available. Determine the TTL LS SSI chip usage for the case of developing a new PCB . iii) The 2-level minimal AND-OR and NAND-NAND circuits require more than one chip each. However, a close analysis of the minimal circuit indicates that only one TTL SSI chip is enough to implement the minimal circuit. Draw that circuit by hand. To determine which chip it is, you can check TTL manuals, such as the On Semiconductor manual or the Motorola manual.
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This note was uploaded on 02/02/2011 for the course CS 2204 taught by Professor Hadimioglu during the Spring '10 term at NYU Poly.

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hw6 - CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN HOMEWORK...

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