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Unformatted text preview: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 48 8) PLS100/PLS101 DESCRIPTION The PLS100 (3-State) and PLS101 (Open Collector) are bipolar, fuse Programmable Logic Arrays (PLAs). Each device utilizes the standard AND/OR/Invert architecture to directly implement custom sum of product equations. Each device consists of 16 dedicated inputs and 8 dedicated outputs. Each output is capable of being actively controlled by any or all of the 48 product terms. The True, Complement, or Don't Care condition of each of the 16 inputs and be ANDed together to comprise one P-term. All 48 P-terms can be selectively ORed to each output. The PLS100 and PLS101 are fully TTL compatible, and chip enable control for expansion of input variables and output inhibit. They feature either Open Collector or 3-State outputs for ease of expansion of product terms and application in bus-organized systems. Order codes are listed in the Ordering Information Table. FEATURES Field-programmable (Ni-Cr link) Input variables: 16 Output functions: 8 Product terms: 48 I/O propagation delay: 50ns (max.) Power dissipation: 600mW (typ.) Input loading: 100A (max.) Chip Enable input Output option: PLS100: 3-State PLS101: Open-Collector PIN CONFIGURATIONS N Package FE* 1 I7 2 I6 3 I5 4 I4 5 I3 6 I2 7 I1 8 I0 9 F7 10 F6 11 F5 12 F4 13 GND 14 28 VCC 27 I8 26 I9 25 I10 24 I11 23 I12 22 I13 21 I14 20 I15 19 CE 18 F0 17 F1 16 F2 15 F3 Output disable function: 3-State: Hi-Z Open-Collector: High * APPLICATIONS CRT display systems Code conversion Peripheral controllers Function generators Look-up and decision tables Microprogramming Address mapping Character generators Data security encoders Fault detectors Frequency synthesizers 16-bit to 8-bit bus interface Random logic replacement Fuse Enable Pin: It is recommended that this pin be left open or connected to ground during normal operation. N = Plastic DIP (600mil-wide) A Package I5 4 I4 I3 I2 I1 I0 5 6 7 8 9 I6 3 I7 FE VCC I8 I9 2 1 28 27 26 25 I10 24 I11 23 I12 22 I13 21 I14 20 I15 19 CE 12 13 14 15 16 17 18 F7 10 F6 11 F5 F4 GND F3 F2 F1 F0 A = Plastic Leaded Chip Carrier ORDERING INFORMATION DESCRIPTION 28-Pin Plastic Dual In-Line 600mil-wide 28-Pin Plastic Leaded Chip Carrier 3-STATE PLS100N PLS100A OPEN COLLECTOR PLS101N PLS101A DRAWING NUMBER 0413D 0401F October 22, 1993 49 8530308 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 48 8) PLS100/PLS101 LOGIC DIAGRAM (LOGIC TERMSP) I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 9 8 7 6 5 4 3 2 27 26 25 24 23 22 21 20 S0 X0 X1 X2 X3 X4 X5 X6 X7 47 40 39 32 31 24 23 1615 8 7 0 S1 S2 S3 S4 S5 S6 S7 18 17 16 15 13 12 11 10 19 F0 F1 F2 F3 F4 F5 F6 F7 CE NOTES: 1. All AND gate inputs with a blown link float to a logic "1". 2. All OR gate inputs with a blown fuse float to logic "0". 3. Programmable connection. October 22, 1993 50 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 48 8) PLS100/PLS101 FUNCTIONAL DIAGRAM I0 TYPICAL CONNECTION I1 I15 TYPICAL CONNECTION S0 F0 S6 F6 S7 F7 P0 P1 P47 CE ABSOLUTE MAXIMUM RATINGS1 SYMBOL VCC VIN VO IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input current Output current Operating temperature range Storage temperature range RATINGS +7.0 +5.5 +5.5 30 +100 0 to +75 65 to +150 UNIT VDC VDC VDC mA mA C C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other conditions above those indicated in the operational and programming specification of the device is not implied. THERMAL RATINGS TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150C 75C 75C The PLS100 device is also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook. October 22, 1993 51 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 48 8) PLS100/PLS101 DC ELECTRICAL CHARACTERISTICS 0C Tamb +75C, 4.75V VCC 5.25V LIMITS SYMBOL Input VIH VIL VIC Output PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT voltage2 High Low Clamp3 voltage2 VCC = MIN VCC = MAX VCC = MIN VCC = MIN, IIN = 12mA 0.8 2.0 0.8 1.2 V V V VOH VOL High Low5 (PLS100)4 IOH = 2mA IOL = 9.6mA 2.4 0.35 0.45 V V Input current IIH IIL High Low VIN = 5.5V VIN = 0.45V <1 10 25 100 A A Output current IO(OFF) Hi-Z state (PLS100) CE = High, VCC = MAX VOUT = 5.5V VOUT = 0.45V IOS ICC Capacitance CE = High, VCC = 5.0V CIN COUT Input Output VIN = 2.0V VOUT = 2.0V 8 17 pF pF Short circuit (PLS100) 3, 6 VCC supply current7 CE = Low, VOUT = 0V VCC = MAX 15 120 1 1 40 40 70 170 A A mA mA NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. All voltage values are with respect to network ground terminal. 3. Test one pin at a time. 4. Measured with VIL applied to CE and a logic high stored. 5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor to VCC. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with the Chip Enable input grounded, all other inputs at 4.5V and the outputs open. October 22, 1993 52 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 48 8) PLS100/PLS101 AC ELECTRICAL CHARACTERISTICS 0C < Tamb < +75C, 4.75 < VCC < 5.25V, R1 = 470, R2 = 1k LIMITS SYMBOL Propagation tPD tCE Disable time tCD Chip Disable3 Output Chip Enable 15 30 ns delay2 Input Chip Enable3 Output Output Input Chip Enable 35 15 50 30 ns ns PARAMETER TO FROM MIN TYP1 MAX UNIT NOTES: 1. All typical values are at VCC = 5V. Tamb = +25C. 2. All propagation delays are measured and specified under worst case conditions. 3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. VOLTAGE WAVEFORMS +3.0V 90% TEST LOAD CIRCUIT VCC 10% +5V S1 0V 5ns +3.0V 90% tR tF 5ns C1 C2 I0 F0 R1 INPUTS 10% 0V 5ns 5ns I15 DUT R2 CL CE GND F7 OUTPUTS MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses NOTE: C1 and C2 are to bypass VCC to GND. TIMING DEFINITIONS SYMBOL tCE PARAMETER Delay between beginning of Chip Enable Low (with Input valid) and when Data Output becomes valid. Delay between when Chip Enable becomes High and Data Output is in off state (Hi-Z or High). Delay between beginning of valid Input (with Chip Enable Low) and when Data Output becomes valid. TIMING DIAGRAM +3.0V INPUT 1.5V 0V +3.0V tCD F0 F7 tPD October 22, 1993 53 tCE tPD CE 1.5V 1.5V 0V tCD VOH 1.5V 1.5V VOL Read Cycle Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 48 8) PLS100/PLS101 LOGIC PROGRAMMING PLS100/PLS101 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP, Data I/O Corporation's ABELTM and Logical Devices Inc.'s CUPLTM design software packages. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLS100/PLS101 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors' SNAP PLD design software package. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The sumbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this dat handbook for additional informational. OUTPUT POLARITY (F) S F X S O, B ACTIVE LEVEL LOW CODE L ACTIVE LEVEL HIGH1 (NON-INVERTING) CODE H (INVERTING) "AND" ARRAY (I) I I I I I I I I I I I I P STATE INACTIVE1,2 CODE O STATE I P CODE H STATE I P CODE L STATE DON'T CARE P CODE "OR" ARRAY (F) P S P S Pn STATUS ACTIVE1 CODE A Pn STATUS INACTIVE CODE NOTES: 1. This is the initial unprogrammed state of all links. It is normally associated with all unused (inactive) AND gates Pn. 2. Any gate Pn will be unconditionally inhibited if any one of its (I) link pairs is left intact. VIRGIN STATE The PLS100/101 virgin devices are factory shipped in an unprogrammed state, with all fuses intact, such that: 1. All Pn terms are disabled (inactive) in the AND array. 2. All Pn terms are active in the OR array. 3. All outputs are Active-High. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 54 CUSTOMER NAME INPUT VARIABLE CF (XXXX) H A NOTES 1. Entries independent of output polarity. 2. Enter (A) for unused outputs of used P-terms. 1. Polarity programmed once only. 2. Enter (H) for all unused outputs. NOTES PROGRAM TABLE ENTRIES OUTPUT FUNCTION Prod. Term Present in Fp (period) H L Prod. Term Not Present in Fp Active High Active Low OUTPUT ACTIVE LEVEL PURCHASE ORDER # Im L (dash) Im Don't Care October 22, 1993 NOTE Enter () for unused inputs of used P-terms. PHILIPS DEVICE # CUSTOMER SYMBOLIZED PART # PROGRAM TABLE TOTAL NUMBER OF PARTS REV 9 8 7 6 5 4 3 2 1 0 11 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 T E R M PROGRAM TABLE # DATE 46 45 44 43 42 41 47 PIN NO. 15 14 13 12 11 10 9 8 VARIABLE NAME Programmable logic arrays (16 48 8) Philips Semiconductors Programmable Logic Devices 20 21 22 23 24 25 26 AND 27 INPUT (Im) 55 2 7 3 6 4 5 5 4 6 3 7 2 8 1 9 0 7 10 6 PLS100/PLS101 11 5 12 4 POLARITY OR OUTPUT (FP) Product specification 13 3 15 2 16 1 17 0 18 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 48 8) PLS100/PLS101 SNAP RESOURCE SUMMARY DESIGNATIONS DIN100 I0 NIN100 I1 I15 AND OR S0 F0 S6 F6 S7 F7 EXOR100 P0 P1 P47 NOE100 CE TOUT100 October 22, 1993 56 ...
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