hw6 - CS2214 COMPUTER ARCHITECTURE & ORGANIZATION...

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HOMEWORK VI CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2010 Polytechnic Institute of NYU Page 1 of 12 Handout No: 15 April 5, 2010 DUE : April 14, 2010 READ : Related Sections of Chapter IV i) Related portions of Chapter 4 (except Section 4.4) ii) Related portions of Appendix B ASSIGNMENT : There are three questions. Solve all homework and exam problems as shown in class and past exam solutions. 1) Consider the following EMY mnemonic machine language program : The EMY CPU is pipelined as explained in class : It has forwardings, delayed branches and write- in-the-first-half, read-in-the-second-half register usage. Assume also that there is a perfect mem- ory, with no stalls. Finally, assume that the ADDI takes five clock periods. The above code is written for the pipelined EMY CPU since independent instructions are placed after the LW and BEQ instructions. The JR instruction takes two clock periods as branch instructions do. The delayed branch concept is also applied to the JR. Thus, the instruction that immediately follows the JR is executed then the instruction pointed by the JR effective address is executed (the instruction pointed by R31). Show the execution of the loop for which you show all the necessary forwarding, register-read- ing-writing and resolved data hazard types as done in class. 400200 LW R8, 0(R4) # R4 initially has 10000000 400204 R9, 4(R4) 400208 R10, 0(R8) 40020C R11, 4(R8) 400210 ADDI R9, R9, (-1) 10 400214 ADD R13, R11, R10 400218 BNE R9, R0, (-5) 10 40021C ADDI R8, R8, 8 400220 JR R31 400224 SW R13, 8(R4) --- --- 10000000 10000400 10000004 2 10000008 ?
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Polytechnic Institute of NYU Page 2 of 12 CS2214 Handout No : 15 April 5, 2010 2) Consider the following EMY mnemonic machine language program : The EMY CPU is pipelined as explained in class : It has forwardings, delayed branches and write- in-the-first-half, read-in-the-second-half register usage. Assume also that there is a perfect mem- ory, with no stalls. Finally, assume that the ADDI takes five clock periods. The code above is written for the unpipelined EMY CPU since there are no independent instruc- tions after the LW and BEQ instructions. i) Reorder the instructions to place independent instructions after the load instruction and in the delayed branch slot. Note that the number of instructions after the reordering will be still six . ii) Show the execution of the loop for two iterations for which you show all the necessary for- warding, register-reading-writing and resolved data hazard types as done in class. iii) Calculate the number of clock periods it takes to run the loop for 100 iterations. 3) Consider the following EMY program : The EMY CPU is pipelined as explained in class : It has forwardings, delayed branches and write- in-the-first-half, read-in-the-second-half register usage. Assume also that there is a perfect mem- ory, with no stalls. Finally, assume that the ADDI takes five clock periods.
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hw6 - CS2214 COMPUTER ARCHITECTURE & ORGANIZATION...

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