hw7 - CS2214 COMPUTER ARCHITECTURE & ORGANIZATION...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
HOMEWORK VII CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2010 Polytechnic Institute of NYU Page 1 of 30 Handout No: 17 April 14, 2010 DUE : April 28, 2010 READ : i) Related portions of Chapter 5 ii) Related portions of Appendix B iv) Related portions of Appendix C ASSIGNMENT : There are eight questions seven of which are from Chapter V of the textbook. Solve all homework and exam problems as shown in class and past exam solutions. 1) Consider the following EMY mnemonic machine language function : The EMY computer has a memory hierarchy now . The addresses the CPU generates are virtual addresses. For simplicity, above, we show the physical addresses , after they are translated from virtual addresses. a) The EMY computer has a physical Level 1 instruction cache and a physical Level 1 data cache each one of which is a 2KB cache with direct mapping and with write-back and write allocate. The block length is 16 bytes. The physical memory contains 16MBytes. For all memory 100 LW R8, 1000(R4) # The LW accesses location 1000 104 R9, 1004(R4) # Read from array B, starting at 1004 108 R10, 2000(R4) # Read from array C, starting at 2000 10C ADDI R4, R4, 4 110 ADD R11, R10, R9 114 ADDI R8, R8, (-1) 10 118 SLTI R12, R8, 0 11C BEQ R12, R0, (-7) 10 120 SW R11, 2FFC(R4) # Store to array A, starting at 3000 124 JR R31 128 NOP --- ---- 1000 0 1004 ? # Starting element of array B --- ---- 2000 ? # Starting element of array C --- ---- 3000 ? # Starting element of array A All addresses are physical addresses
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Polytechnic Institute of NYU Page 2 of 30 CS2214 Handout No : 17 April 14, 2010 addresses generated, clearly show which instruction/data is mapped to which block of which cache. Then, assume that it is a cold start and indicate chronologically if there is a cache miss or hit, if a block is replaced and if a block is written back to the physical memory, for all memory accesses generated : b) Assume for this part that the EMY CPU is pipelined as discussed in class. Assume that the L1 cache memories take one (1) clock period when there is a hit. When there is a miss, the latency is four (4) clock periods and transferring a 4-byte item takes 1 clock period each. Based on part (a) , clearly show in which clock period the last cycle of the instruction that follows the JR instruction is performed as done in class, i.e. together with all the necessary forwarding, register-reading-writing and resolved data hazard types as done in class. c) The EMY main memory is 8-way low-order interleaved. Clearly show which instruction and data are stored in which location of which memory bank. Show how the cache blocks in part (a) are mapped to the memory banks. d) The EMY virtual memory has 2 32 bytes. Assume that the above subroutine starts at virtual address 400100 and R4 has 10000000. The page length of the EMY computer is 4KBytes. For the two caches, the EMY has two TLBs, each with 64 entries and 4-way block set associative mapping with FIFO. Assume that when the CPU makes memory references there are always TLB hits, i.e. the TLBs always contain the physical page number of virtual pages. Show which set and which block of which TLB contains the entries and also show the important fields of the page table entries after the code completes.
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/02/2011 for the course CS 2214 taught by Professor Hadimioglu during the Spring '10 term at NYU Poly.

Page1 / 30

hw7 - CS2214 COMPUTER ARCHITECTURE & ORGANIZATION...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online