hw1 - CS 6143 COMPUTER ARCHITECTURE II HOMEWORK I FALL 2010...

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CS 6143 COMPUTER ARCHITECTURE II FALL 2010 HOMEWORK I Polytechnic Institute of NYU Page 1 of 16 Handout No : 2 September 8, 2010 DUE : September 29, 2010 READ : - Related portions of Chapters 1, 2, 3 and Appendix A and Appendix B of the Hennessy book - Related portions of Chapters 1 and 7 of the Jordan book ASSIGNMENT: There are three problems. Solve all homework and exam problems as shown in class and past exam solutions. 1) Consider the following piece of MIPS code : Note that this code is a function and the JR instruction is used to return from the function. The JR takes two clock periods as branch instructions do. The delayed branch concept is also applied to the JR. Thus, the instruction that follows the JR (the S.D. in location 228 above) is executed after JR. Then, the instruction pointed by the JR effective address is executed (the instruction pointed by R31). Note that the compiler could not find an independent instruction for the BNEZ delay slot and so had to place a “DADD R10, R10, R0” instruction that is equivalent to a NOP instruction. The NOP instruction is pointed by an arrow above. Also, location 22C does not have an instruction. That is, it is not used. a) Write the corresponding piece of high-level code in the style of class discussions and also by using the names of variables mentioned in the comment section above. 200 LD R8, 230(R0) 204 LD R9, 238(R0) 208 L.D F1, 0(R8) ; Load “k” 20C L.D F2, 8(R8) ; Load an element of A 210 DADDI R8, R8, #8 ; Update the A pointer 214 MUL.D F1, F1, F2 ; Multiply “k” and A[i] 218 DADDI R9, R9, #(-1) 10 ; Decrement the loop end counter 21C BNEZ R9, (-5) 10 ; The end of the loop ? 220 DADD R10, R10, R0 ; A NOP instruction 224 JR R31 ; Return from the function 228 S.D F1, 240(R0) ; Store the result in p 22C --- ; This location is not used 230 400 238 2 240 ?
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Polytechnic Institute of NYU Page 2 of 16 CS6143 Handout No : 2 September 8, 2010 b) Assume that this is the machine model number 2 (the MIPS Int+FP pipeline) and the Figure 2.2 latencies are applicable. Clearly show in which clock period the last cycle of the S.D after the JR instruction is performed as done in lecture presentations, i.e. together with all the necessary for- warding and write-in-the-first-half-read-in-the-second-half cases. Assume that the L1 cache memories take one clock period each and there are no cache misses. c) Repeat part (b), by assuming that the L1 cache memories take three (3) clock periods each and there are no cache misses. d) Repeat part (b), by assuming that the L1 cache memories experience cache misses. Assume that all the addresses in the code are physical addresses and the memory hierarchy is as described on slide 104 of the MIPS CPU PowerPoint presentation. Assume that it is a cold start. Clearly show in which clock period the last cycle of the S.D after the JR instruction is performed as done in lecture presentations, i.e. together with all the necessary forwarding and write-in-the-first-half-read-in-the-second-half cases.
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This note was uploaded on 02/02/2011 for the course CS 6143 taught by Professor Hadimioglu during the Fall '10 term at NYU Poly.

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hw1 - CS 6143 COMPUTER ARCHITECTURE II HOMEWORK I FALL 2010...

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