Polytechnic Institute of NYU
Handout No : 5
September 22, 2010
October 13, 2010
‚ Related portions of Chapters 2, 3 and Appendix A of the Hennessy book
‚ Related portions of Chapter 7 of the Jordan book
Solve all homework and exam problems as shown in class and past exam solutions
Consider the piece of code studied in Problem 4 of Homework I.
This code is for the
application we discussed in class :
Assume that this is
machine model number 3
: The MIPS uses the
Hennessy book and as discussed class.
Additional assumptions are as follows : The functional
unit timings are as listed on
of the Hennessy book : ADD.D, MUL.D and DIV.D take 3, 11
and 41 clock periods, respectively ; the number of reservation station buffers for FP operations is
as given in class ; there are enough number of CDB buses to eliminate bottlenecks ; Branch
instructions take 2 clock periods, but there is
delayed branch ; there are enough functional
units for integer instructions not to cause stalls ; Store instructions complete in the WR stage ;
there is a
memory with no stalls.
In which clock period, will the second iteration of the loop be completed, assuming there are just
two iterations ?
That is, what is the last clock period in which the Write-Result stage of an
instruction from the
iteration be done.
Show the forwardings and write-in-the-first-half-
read-in-the-second-half cases among the instructions.
To answer the question, continue with the
following table :
F0, F0, F2
4/5 - 15
; load X[i]
F0, F0, F2
; multiply a * X[i]
; load Y[i]
F0, F0, F4
; add a * X[i[ + Y[i]
; store Y[i]
R1, R1, #(-8)
; decrement X index
R2, R2, #(-8)
; decrement Y index
; loop if not done