hw3 - CS 6143 COMPUTER ARCHITECTURE II HOMEWORK III FALL...

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CS 6143 COMPUTER ARCHITECTURE II FALL 2010 HOMEWORK III Polytechnic Institute of NYU Page 1 of 22 Handout No : 6 October 6, 2010 DUE : October 20, 2010 READ : ‚ Related portions of Chapters 2, 3 and Appendces A, F and G of the Hennessy book ‚ Related portions of Chapter 7 of the Jordan book ASSIGNMENT: There are four problems three of which are developed from the Hennessy book. Solve all homework and exam problems as shown in class and past exam solutions 1) Consider the piece of code studied in Problem 3 of Homework I. This code is for the DAXPY application we discussed in class : Assume that the MIPS is implemented as the 2-way superscalar hardware-speculative Toma- sulo algorithm machine as discussed in class. That is, this is machine model number 5. A pair of instructions is issued per cycle, provided that static issuing is preserved. Two (2) instructions can be committed in order per cycle provided that they are at the head of the ROB. a) Assume also that the functional unit timings are as listed on page A-72 of the Hennessy book ; the number of reservation station buffers for FP operations is as given in class ; the number of CDB buses is as given class ; there is a Branch Unit in the EX stage for calculating its effective address and determining the condition ; there is also additional branch prediction hardware in and out of the pipeline ; there are enough functional units for integer instructions not to cause stalls ; the L1 cache memories take one clock period each and there are no cache misses ; the L1 data cache memory allows two memory accesses for data per clock period if there are no address con- flicts. Assume that there is only one iteration. Then, in which clock period, will the first iteration of the above loop be completed ? That is, what is the last clock period in which the Commit stage of an instruction from the first iteration be done last ? Also, show which instructions are flushed out of the pipeline. Indicate any assumptions made during the execution of the loop, if a situation not discussed in class is encountered. To answer it, continue the following table : loop : L.D F0, 0(R1) ; load X[i] MUL.D F0, F0, F2 ; multiply a * X[i] L.D F4, 0(R2) ; load Y[i] ADD.D F0, F0, F4 ; add a * X[i[ + Y[i] S.D F0, 0(R2) ; store Y[i] DADDI R1, R1, #(-8) 10 ; decrement X index DADDI R2, R2, #(-8) 10 ; decrement Y index BNEZ R1, loop ; loop if not done
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Polytechnic Institute of NYU Page 2 of 22 CS6143 Handout No : 6 October 6, 2010 b) Repeat part (a), by assuming that the L1 cache memories take four (4) clock periods each and there are no cache misses. Assume that the memory hierarchy is as described in the MIPS CPU PowerPoint presentation. Do not show which instructions are flushed from the pipeline. But, show the forwardings and write-in-the-first-half-read-in-the-second-half cases among the instruc- tions.
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hw3 - CS 6143 COMPUTER ARCHITECTURE II HOMEWORK III FALL...

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