Lab5 - Name G Number Laboratory#Binary Adder Circuits ECE...

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Name: G Number: Laboratory #Binary Adder Circuits ECE 332 1 Introduction In this laboratory you will design and simulate a Half Adder, Full Adder using TTL gates and simulate the functionality of Half and Full adders and a 4-bit ripple carry adder on the Cool Runner-2 CPLD board. Parts of this have already been completed in the pre-lab. 2 Design and Simulate a Half and Full Adder In the pre-lab you designed a Half and Full adder. In lab you will complete this design and simulate its functionality using TTL gates. You will be expected to complete the following items as part of this experiment: 1. Completed Truth Table, derive the equations for Half adder (pre-lab) 2. Draw the circuit diagram for a Half Adder (pre-lab) 3. Draw the circuit diagram for a Full Adder implemented using two half adder (pre-lab) 4. Read up and draw the circuit diagram for a 4-bit Ripple carry adders using full adders (pre- lab) 5. Implement Half Adder using TTL gate 6. Implement Full Adder using two half adders using TTL gate 7. Write the VHDL code for a Half, Full and a 4-bit Ripple carry adder and implement it on
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