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Unformatted text preview: Name: G Number: Laboratory #Propagation Delay and Power Measurement ECE 332 1 Introduction In this lab you are going to observe the propagation delay 2-input AND gate implemented using a TTL IC and a 2-input AND gate implemented in CPLD and compare per gate propagation delay in both technologies. You are also going to measure power consumption of the CPLD when it is implementing the propagation delay circuit at run time. 2 Propagation Delay in TTL technology Connect the four gates present in 74LS08 Quad2-input AND gate IC as shown in circuit diagram 1. Connect one input of the first AND gate(leftmost) to a square wave or clock source present on the trainer. Tie the second input to 1 i.e. VCC. Connect the output of the final AND gate(right most) to the oscilloscope. Connect clock source to channel 1 and the output from the AND gate to channel 2 of the oscilloscope so that you can visualize the propagation delay easily. Observe the propagation delay as the output of circuit 2 changes from 0 to 1. Note down the propagation delaypropagation delay as the output of circuit 2 changes from 0 to 1....
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- Fall '08