Lab8 - Name: G Number: Laboratory #Multiplexers and...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Name: G Number: Laboratory #Multiplexers and Demultiplexers ECE 332 1 Introduction In this laboratory you will explore the functionality of Multiplexers or Muxes and De-Multiplexers or De-mux on the Cool Runner-2 CPLD board. Parts of this have already been completed in the pre-lab. 2 Design of Mux and DeMux Circuit In the prelab you derived the Truth Table for a 4 x 1 Mux and a 2-to-4 Decoder. In addition, you realized a 2-to-4 Decoder using a 1 x 4 De-Mux. In lab you will complete the design of the circuit shown in Figure 1 and simulate its functionality on the CPLD board. You will be expected to complete the following items as part of this experiment: 1. Completed Truth Table of a 4x1 Mux (pre-lab) 2. Completed Truth Table of a 2 to 4 Decoder (pre-lab) 3. Completed Truth Table of a 1 x 4 De-mux (pre-lab) 4. VHDL code for the 2-bit counter and the clock-select circuit (Provided by T.A) 5. VHDL code for a 4-bit BCD to 7 Segment Decoder (From Lab-4) 6. Write the VHDL code for Circuit diagram shown in Figure 1 and implement it on the CPLD
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/02/2011 for the course ECE 332 taught by Professor Staff during the Fall '08 term at George Mason.

Page1 / 3

Lab8 - Name: G Number: Laboratory #Multiplexers and...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online