Lab9 - Write the VHDL code for the following • Gated S-R Latch • J-K Flip-Flop • D Flip-Flop • T Flip-Flop 3 Submissions for Lab 1 Attach

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Name: G Number: Laboratory #Latches and Flip-Flops ECE 332 1 Introduction In this laboratory you will explore the functionality of Latches and Flip-Flops on the Cool Runner-2 CPLD board. Parts of this have already been completed in pre-lab: 1. Completed Circuit diagram and Truth table for Gated S-R Latch, J-K Flip-Flop, D Flip-Flop. (pre-lab) Parts to be completed in lab: 1. Completed Circuit diagram and Truth table for T Flip-Flop. 2. Write the VHDL code for for Gated S-R Latch, J-K Flip-Flop, D Flip-Flop and T Flip-Flop and implement it on the CPLD board 2 Circuit to be implemented as a part of Lab
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Unformatted text preview: Write the VHDL code for the following: • Gated S-R Latch • J-K Flip-Flop • D Flip-Flop • T Flip-Flop 3 Submissions for Lab 1. Attach the following waveforms • Post-Fit waveform. 2. Report Following Parameters: • Cell Usage from Synthesis Report. • VHDL code for entire circuit including your new package/components (you don’t need to submit the package ±le already provided to you) • Resource Summary From Fitter report. 3. You have to write the UCF ±le. Best of Luck!! 1...
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This note was uploaded on 02/02/2011 for the course ECE 332 taught by Professor Staff during the Fall '08 term at George Mason.

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