Unformatted text preview: Write the VHDL code for the following: • Gated S-R Latch • J-K Flip-Flop • D Flip-Flop • T Flip-Flop 3 Submissions for Lab 1. Attach the following waveforms • Post-Fit waveform. 2. Report Following Parameters: • Cell Usage from Synthesis Report. • VHDL code for entire circuit including your new package/components (you don’t need to submit the package ±le already provided to you) • Resource Summary From Fitter report. 3. You have to write the UCF ±le. Best of Luck!! 1...
View Full Document
- Fall '08
- Logic gate, Field-programmable gate array, CPLD, Gated S-R Latch