M216A_1_Sample-Midterm

M216A_1_Sample-Midterm - Electrical Engineering M216A...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Electrical Engineering M216A Sample Midterm _________________________ Name (Last, First) Please write answers in the box provided. Answers elsewhere will not be graded. 1.(8)_______ 2.(20)_______ 3.(12)_______ 4.(20)_______ 5.(20)_______ Score________ (80 points) You have 90 minutes. The test is planned so that you’ll spend roughly one point per minute. Good Luck!
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
1. (8) Power and Delay (a) If V DD decreases, does the output rising (t pLH ) delay of a static CMOS gate (b) If V DD decreases, does the output falling (t pHL ) delay of a static CMOS gate (c) If V DD decreases, does the energy consumption of a CMOS gate (d) If V DD decreases, does the energy-delay product (use the average rise/fall delay) 2. (20) Static CMOS Gate design A function is described in the following Karnaugh map. Write the function, f (use the don’t care states, ‘-’, where needed) using the minimum number of terms and literals. Imple- ment the function with a single static CMOS gate and minimize the number of transis- tors . True and complement of inputs are available.
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 7

M216A_1_Sample-Midterm - Electrical Engineering M216A...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online