{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

M216A_1_final_exam04_soln

# M216A_1_final_exam04_soln - 1(20 Logical Effort(a(5...

This preview shows pages 1–3. Sign up to view the full content.

Electrical Engineering M216A Final Exam December 15, 2004 _______Solutions_____ Name (Last, First) _________________________ Student ID # (closed book/2 8.5x11 pages are permitted) You will need a calculator Please write answers in the box provided. Answers elsewhere will not be graded. GOOD LUCK! 1.(____/20) 2.(____/12) 3.(____/10) 4.(____/8) 5.(____/15) 6.(____/20) ______/85 1. (20) Logical Effort (a) (5) Determine the logical effort of this AOI gate, for all inputs. Assume that β=µ=µ N P = 3 (b) (4) Determine the parasitic effort of input a . Assume that C diff = 0.5C gate and no sharing of diffusions. (c) (3) Determine the parasitic effort of input c with the same assumptions as in (b). Include the internal nodes of the gate in your calculations. Answer: g a = 18/16 = 1.125 12 6 18 36 12 12 a a b b c c out g b = 30/16 = 1.875 g c = 48/16 = 3 key points: correct methodology reference inverter calculation Answer: p a_up = 36/32=1.125 p a_dn = 36/32 key points: correct methodology adjustment for Cdiff not equalling Cgate accounting for diffusions no internal nodes (because of a input) Answer: p c_up = 1.71 p c_dn = 1.437 5 6/(3*16*2)+36/(16*2) = pup 30/(3*16*2) + 36/(16*2) = pdown key points: correct methodology proper accounting for internal nodes

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
(d) (4) Determine the logical effort of the a input if the β= 1.7 for the reference inverter. (e) (4) Determine the logical effort of the b input if we account for velocity saturation. The reference inverter has β= 2 and R Pno_stack =1.2R P_stacked , R Nno_stack =1.33R N_stacked . Assume that the values given already accounts for the effect of unequal stack sizes. 2. (12) Adder Design (a) (5) The PG network of a 16-bit Han-Carlson adder is shown below. Write the expressions for the logic performed by the two types of boxes. You can assume that the inputs from the top for each bit position (n) is P n and G n . Answer: g a_up = 0.94 g a_dn = 1.67 g a_up = (12+6)/(12(1+1/1.7) g a_dn = (12+6)/(4(1+1.7)) key points: correct methodology proper reference inverter separate calculation for up and dn. Answer: g b_up = 1.39 g b_dn = 1.88 g b_up = 30/(12*1.2*(1 + 1/ β )) g b_dn = 30/(4*1.33*(1+ β )) key points: proper reference inverter calculation adjustment for velocity saturation Answer: functions (dark box) −−> G MN = G MK P KN + G KN ; P MN = P MK P KN
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### What students are saying

• As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

Kiran Temple University Fox School of Business ‘17, Course Hero Intern

• I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

Dana University of Pennsylvania ‘17, Course Hero Intern

• The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

Jill Tulane University ‘16, Course Hero Intern