M216A_1_final_exam04

M216A_1_final_exam04 - Electrical Engineering M216A Final...

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Unformatted text preview: Electrical Engineering M216A Final Exam December 15, 2004 _________________________ Name (Last, First) _________________________ Student ID # (closed book/2 8.5x11 pages are permitted) You will need a calculator Please write answers in the box provided. Answers elsewhere will not be graded. GOOD LUCK! 1.(____/20) 2.(____/12) 3.(____/10) 4.(____/8) 5.(____/15) 6.(____/15) ______/80 1. (20) Logical Effort (a) (5) Determine the logical effort of this AOI gate, for all inputs. Assume that β=µ=µ N /µ P = 3 (b) (4) Determine the parasitic effort of input a . Assume that C diff = 0.5C gate and no sharing of diffusions. (c) (3) Determine the parasitic effort of input c with the same assumptions as in (b). Include the internal nodes of the gate in your calculations. Answer: g a = 12 6 18 36 12 12 a a b b c c out g b = g c = Answer: p a_up = p a_dn = Answer: p c_up = p c_dn = (d) (4) Determine the logical effort of the a input if the β= 1.7 for the reference inverter. (e) (4) Determine the logical effort of the b input if we account for velocity saturation. The reference inverter has β= 2 and R Pno_stack =1.2R P_stacked , R Nno_stack =1.33R N_stacked . 2. (12) Adder Design (a) (5) The PG network of a 16-bit Han-Carlson adder is shown below. Write the expressions for the logic performed by the two types of boxes. You can assume that the inputs from the top for each bit position (n) is P n and G n ....
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This note was uploaded on 02/06/2011 for the course EE M216A taught by Professor Marković during the Spring '08 term at UCLA.

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M216A_1_final_exam04 - Electrical Engineering M216A Final...

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