20085eeM216A_1_Hw4-F08-Sol

# 20085eeM216A_1_Hw4-F08-Sol - Electrical Engineering...

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Electrical Engineering Department Fall 2008 1 EEM216A – Design of VLSI Circuits and Systems Homework #4 Solution D. Markovic Problem 1: Timing Analysis a) Single-phase clocking / Time borrowing A single-phase clocking system is shown below. Assume t D-Q = t setup = t Clk-Q = 0, t hold = 0.5. What is the minimum pulse width needed for this system to work properly? What is the maximum allowable pulse width? The delay of each path is indicated as (min, max). The clock period is 7. SOLUTION Minimum pulse width needed to be able to borrow the time for the longest path delay. Longest path is 8, while clock period is 7. T cycle + T W > max(t p ) + t setup + t Clk Q T W > 8 + 0 7, T W > 1 Maximum pulse width must satisfy hold time for minimum delay. T W + t hold < min(t p ) + t Clk Q (+ t borrowed ) Check delay path of 2; T W < 2 + 0 0.5 = 1.5 Check delay path of 1.5 (since the previous stage borrowed 1ns); T W < 1.5 + 0 + (1) 0.5 = 2.0 Worst case is T W < 1.5 b) Two-phase clocking / Time borrowing In the design shown below, delay of each path is (min, max). Assume t D-Q = t Clk-Q = 0.25, t setup = 0, t hold = 0.25. What is the minimum cycle time? Based on this cycle time, assuming that rising clock edges are T cycle /2 apart, what is pulse width of the clock you would choose to absorb the most clock skew between Φ 1 and Φ 2 ?

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Electrical Engineering Department Fall 2008 2 SOLUTION Minimum cycle time must be when the maximum delay is less than 1 cycle. T cycle > max(t p1 ) + max(t p2 ) + 2t D Q T cycle > 3.5 + 2.0 + 0.5; T cycle > 6.0 Check the bounds on the pulse width. Pulse width must be large enough for time borrowing. T W + T cycle /2 > max(t p ) + t D Q T W > 3.5 + 0.25 6/2; T W > 0.75 For hold time violation, pulse width must not be excessively large. min(t p ) + t Clk Q > T W T cycle /2 + t hold 1 + 0.25 > T W 3 + 0.25; T W < 4.0 T W opt = 0.5*(T W min + T W max ) = 2.375 ( can handle < 1.625 skew ) c) Flip-flop based design The design shown below uses edge-triggered clocking. Assume t Clk-Q = 0.4, t setup = 0.2, t hold = 0.1. What is the minimum clock cycle time with zero clock skew? What is the maximum clock skew that the scheme can tolerate while running with a clock period of 10? SOLUTION Minimum cycle time depends on the maximum propagation delay.
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20085eeM216A_1_Hw4-F08-Sol - Electrical Engineering...

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