Electrical Engineering Department
Fall 2008
1
EEM216A – Design of VLSI Circuits and Systems
Homework #3
Solution
D. Markovic
Problem 1:
Delay and Energy Capacitance
In this problem we have to determine linear equivalent of the inverter input capacitance using Spectre.
Use simulation setup similar to the one discussed in class.
All inverters are INVX1.
To develop models
for supply voltage optimization, do the following for V
DD
= 0.4V, 0.7V, and 1.0V.
a) Determine capacitance C
D
from the simulation setup to match propagation delays of the inverter
loaded with another identical inverter (include extra stage to suppress Miller capacitance).
b) Determine capacitance C
E
in such a way as to match energy of the two inverters from the simulation
setup.
Calculate energy by integrating current through V
DD
.
c)
Based on signal slopes from (1a) and transistor thresholds from homework 1, estimate the capacitance
C
SC
that corresponds to shortcircuit energy dissipation.
Discuss C
SC
/ C
E
(V
DD
).
d) Are C
D
and C
E
different?
How does V
DD
affect results?
Comment your results.
SOLUTION
(1a) & (1b)
Capacitance values are obtained by simulation as shown in
lecture 3
(
slide 40
).
Figure 1
illustrates the estimation method for a fixed V
DD
(1V in this case).
1.5
1.7
1.9
2.1
2.3
2.5
10
12
14
16
18
20
C (fF)
Delay (ps)
C
D
= 1.95 fF
1.5
2
2.5
3
3.5
4
4.5
2
3
4
5
C (fF)
Energy (fJ)
C
E
= 2.45 fF
C
Ec
= 3.95 fF
Figure 1.
Simulated delay (left) and energy (right) versus capacitance.
Plot on the right estimates two values: C
E
represents energy on the gate capacitance, C
Ec
represents energy stored on gate and parasitic capacitances.
In
both cases, we are matching energy dissipated from V
DD
of the test gate.
Discussion:
The difference between C
E
and C
Ec
is that C
E
considers gate capacitance only, while C
Ec
lumps
both C
gate
and C
parasitic
.
In fact, we can use these values to estimate
γ
as
γ
= (C
Ec
– C
E
)/C
E
= 0.61.
As you
may expect, this matches our result from
homework 2
,
problem 1c
.
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Electrical Engineering Department
Fall 2008
2
Cap / V
DD
0.4 V
0.7 V
1.0 V
C
D
(fF)
1.5
1.7
1.9
C
E
(fF)
2.1
2.2
2.4
(1c)
Short
‐
circuit power exists when both NMOS and PMOS are “on” simultaneously during a single
switching transition.
For the output
‐
rising transition, we can assume that PMOS is “on” and that NMOS
is linear (V
out
close to 0).
For the output
‐
falling transition, we can assume that NMOS is “on” and that
PMOS is linear (V
out
close to V
DD
).
Strategy:
Approximate short
‐
circuit current with a triangular current waveform.
Given the slope values
from previous homeworks, we can approximate t
SC
as the time spent between V
tn
and V
DD
+ V
tp
.
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 Spring '08
 Marković
 Electrical Engineering, Energy, Vdd, Delay, Electrical Engineering Department

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