20085eeM216A_1_Hw2-F08-Sol

# 20085eeM216A_1_Hw2-F08-Sol - Electrical Engineering...

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Electrical Engineering Department Fall 2008 1 EEM216A – Design of VLSI Circuits and Systems Homework #2 Solution D. Markovic Problem 1: Delay Model Calibration In this problem, we are going to extract parameters for logical effort analysis. The objective is to find the self-loaded (i.e. no external capacitive load, just the internal capacitances) delay of an inverter fabricated in our 1V 90nm process. This delay cannot be simply measured in Spectre with a single unloaded inverter due to problems with Miller multiplication and capacitive coupling. So first, set up the schematic as in Fig. 1 to simulate the multi-stage inverter chain (with fanout f ): V in 11 f- 1 f ( f- 1) 1 f- 1 f ( f- 1) 1 f- 1 f ( f- 1) f t p,FOf Figure 1. Test setup for delay versus fanout simulation. Assume pulse waveform at V in (t rise/fall = 50ps). Unit inverter (“1”) is INVX1 from std-cell library. Using this circuit, you can get accurate measurement of delay by measuring the delay of the third inverter in the chain. The first two stages create a realistic input signal slope to the third inverter. The fourth stage provides an appropriate load for the third stage. The last stage is just for good measure, to make sure that the Miller effect for the fourth stage is reasonable. In order to get the self-loaded delay, do the following for V DD = 0.4V, 0.7V, and 1.0V: a) Use Spectre to find the average propagation delay t p = (t pLH + t pHL )/2 for an inverter in this process for a fanout of 2 to 10 in increments of 1. Simply measure the delay of the third inverter in this chain. Plot the propagation delay as a function of fanout. b) In the plot from (1a), the points should fall on a straight line. Find the best linear fit and extrapolate the delay for fanout = 0. The intercept defines the self-loaded delay t p0 . c) In the plot from (1a), the slope of the line tells you about the additional delay per fanout. Assuming g inv = 1, determine parameter γ from the logical effort theory. d) Based on results from (b) and (c), and using the time constant at V DD = 1V, propose a logical effort model that includes the impact of V DD scaling. Hint: alpha-power model would be a reasonable starting point. e) Measure the transition time as a function of fanout. The transition time is the average of rising and falling transition times, with respect to 10% and 90% points. Tabulate transition times with respect to fanout for all V DD values. This result will later be useful for signal slope correction in gates with unequal input and output slopes.

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Electrical Engineering Department Fall 2008 2 SOLUTION Simulation results and extracted parameters are shown below. 0 2 4 6 8 10 0 20 40 60 80 100 fanout Delay (ps) t p0 = 4.84 ps γ = 0.61 0 2 4 6 8 10 0 50 100 150 200 fanout t p0 = 8.28 ps γ = 0.60 0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 fanout Delay (ns) t p0 = 63.82 ps γ = 0.50 Figure 1a1. V DD = 1V Figure 1a2. V DD = 0.7V Figure 1a3. V DD = 0.4V V DD (V) 1b) t p0 (ps) 1c) γ = C par / C in t p0 / (ps) 1.0 4.8 0.61 7.9 0.7 8.3 0.60 13.8 0.4 63.8 0.50 127.6 U sing lsqcurvefit function in Matlab, the intercept point (1b) and parasitic delay (1c) are obtained by forcing the logical effort to 1. The last row in the table estimates
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## 20085eeM216A_1_Hw2-F08-Sol - Electrical Engineering...

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