20085eeM216A_1_Hw1-F08-Sol

20085eeM216A_1_Hw1-F08-Sol - Electrical Engineering...

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Electrical Engineering Department Fall 2008 1 EEM216A – Design of VLSI Circuits and Systems Homework #1 Solution D. Markovic The goal of this assignment is to get familiar with the 90nm CMOS technology we use in class, and to study technology scaling. Problem 1: MOS Transistor Models a) Using Spectre, generate the family of I-V curves ( help : online Tutorial 1 from EE115C has detailed instructions on how to do this) for NMOS and PMOS transistor with the following parameters: (W/L) n = 430nm/100nm, (W/L) p = 650nm/100nm Sweep |V DS | from 0V to 1V in 50mV increments |V GS | = 0.4V, 0.5V, 0.7V, 1.0V |V SB | = 0V, 0.5V Use the 90nm model as instructed in Tutorial 1 (section NN in the transistor model). Plot all I-V curves on one graph for NMOS and another graph for PMOS. Label bias conditions for V GS and V SB . SOLUTION Strategy: follow Tutorial 1 from EE115C to learn how to generate MOS I V curves. The results could be exported to Excel / Matlab environment for further analysis or display. Matlab plots are show below. Tip: you may use Excellink add on in Excel to interface with Matlab – see the link at classwiki… 0 0.2 0.4 0.6 0.8 1 0 50 100 150 200 250 300 V DS (V) NMOS I D ( µ A) 0 0.2 0.4 0.6 0.8 1 0 50 100 150 200 250 300 V DS (V) PMOS I 1V 0 .7 V 0.5V 0.4V 0.7V 1 |V SB | = 0V |V SB | = 0.5V NMOS W = 430n L = 100n PMOS W = 650n L = 100n Figure 1a. Transistor I V curves (absolute V DS value for PMOS shown). Device size corresponds to 1x inverter from standard cell library. Drain current I D decreases with reverse body bias (dashed).
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Electrical Engineering Department Fall 2008 2 Universal model b) Based on the results from the previous part, determine the following model parameters: V T0 , µ , λ , γ . ( hint : you don’t need to know V DSAT ) You may assume that 2 Φ F = -0.6V. Which parts of the I-V characteristic are the most important to be matched? ( hint : extract λ parameter from the velocity saturation curves) Determine the parameter values for both NMOS and PMOS. In the universal analytical model, assume that the effective channel length is L eff =70nm (in order to approximate behavior of a device with a length of 100nm obtained by Spectre simulations). SOLUTION There are multiple ways to extract device parameters. A simple method follows. 1b1) Extracting threshold voltage, V T0 Rationale: since V DSAT is not available, we have to extract V T0 from the saturation region. Strategy: select two points in the saturation region from different V GS curves, (V BS = 0) and the same V DS in both cases (e.g. V DS = 0.6V). Assume that the device is in saturation for V GS = 0.4V and V GS = 0.5V. Exact values for the points from part 1a are obtained from Spectre simulation / Excel table. 50 0 0 0.2 0.4 0.6 0.8 1 I D ( µ A) V DS (V) V GS = 0.4V V GS = 0.5V SATURATION B A Figure 1b1. Two point method for extracting V T0 parameter. V T0 is calculated from the universal model and saturation device. Use the saturation model to solve for V T0 : Æ Æ For V SB = 0, V T = V T0 . Calculated values for NMOS and PMOS are reported below: Device V T0 (VB = 0V) V T (VB = 0.5V) NMOS 165mV 208mV PMOS 216mV 274mV 1b2) Extracting body effect parameter, γ Using the results from V T extraction, we calculate the body
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This note was uploaded on 02/06/2011 for the course EE M216A taught by Professor Marković during the Spring '08 term at UCLA.

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20085eeM216A_1_Hw1-F08-Sol - Electrical Engineering...

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