20085eeM216A_1_Hw4-F08

20085eeM216A_1_Hw4-F08 - Electrical Engineering Department...

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Electrical Engineering Department Fall 2008 EEM216A – Design of VLSI Circuits and Systems Homework #4 Due Friday, November 21, 2pm (Hw drop box) MSOL students: email to [email protected] Problem 1: Timing Analysis a) Single-phase clocking / Time borrowing A single-phase clocking system is shown below. Assume t D-Q = t setup = t Clk-Q = 0, t hold = 0.5. What is the minimum pulse width needed for this system to work properly? What is the maximum allowable pulse width? The delay of each path is indicated as (min, max). The clock period is 7. b) Two-phase clocking / Time borrowing In the design shown below, delay of each path is (min, max). Assume t D-Q = t Clk-Q = 0.25, t setup = 0, t hold = 0.25. What is the minimum cycle time? Based on this cycle time, assuming that rising clock edges are T cycle /2 apart, what is pulse width of the clock you would choose to absorb the most clock skew between Φ 1 and Φ 2 ? c)

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20085eeM216A_1_Hw4-F08 - Electrical Engineering Department...

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