20085eeM216A_1_Hw2-F08

20085eeM216A_1_Hw2-F08 - Electrical Engineering Department...

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Electrical Engineering Department Fall 2008 EEM216A – Design of VLSI Circuits and Systems Homework #2 Due Friday, October 24, 2pm (Hw drop box) MSOL students: email to [email protected] Problem 1: Delay Model Calibration In this problem, we are going to extract parameters for logical effort analysis. The objective is to find the self-loaded (i.e. no external capacitive load, just the internal capacitances) delay of an inverter fabricated in our 1V 90nm process. This delay cannot be simply measured in Spectre with a single unloaded inverter due to problems with Miller multiplication and capacitive coupling. So first, set up the schematic as in Fig. 1 to simulate the multi-stage inverter chain (with fanout f ): V in 11 f- 1 f ( f- 1) 1 f- 1 f ( f- 1) 1 f- 1 f ( f- 1) f t p,FOf Figure 1. Test setup for delay versus fanout simulation. Assume pulse waveform at V in (t rise/fall = 50ps). Unit inverter (“1”) is INVX1 from std-cell library. Using this circuit, you can get accurate measurement of delay by measuring the delay of the third inverter in the chain. The first two stages create a realistic input signal slope to the third inverter.
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This note was uploaded on 02/06/2011 for the course EE M216A taught by Professor Marković during the Spring '08 term at UCLA.

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20085eeM216A_1_Hw2-F08 - Electrical Engineering Department...

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