M216A_1_Lec-07-Dynamic-Power-n2

M216A_1_Lec-07-Dynamic-Power-n2 - EEM216A Fall 2008 Lecture...

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Low Power Design: Active Power EEM216A – Fall 2008 Lecture 7 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 ± Crucial for Portable Applications Determines battery lifetime Increased amount of computation ± Crucial for High-Performance Applications Determines cooling and energy costs Many designs today are power limited Still need maximum performance The Importance of Power Awareness
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EEM216A / Fall 2008 D. Markovic / Slide 3 The Power Challenge IBM RoadRunner [2008] ± Top supercomputer (PFlop) 122400 cores PowerXCell 8i 3.2 GHz/ Opteron DC 1.8 GHz 1,375,776 GFlops (peak) ± $100M ± Technical specs 12,240 Cell chips 6,562 AMD Opteron chips 98 TB of memory 278 racks (5,200 square feet) 55 miles of fiber optic cable 500,000 lbs 2.35 MW 437 M calculations / W ± Future data centers 1000 PFlops (~2015) Climate modeling Human genome science Limited (today) to ~20 MW due to power distribution issues EEM216A / Fall 2008 D. Markovic / Slide 4 Where Does the Power Go? Power Delivery Computation Memory Cooling (AC) Storage Courtesy: P. Franzon, NCSU 10 MW 10 MW
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EEM216A / Fall 2008 D. Markovic / Slide 5 Where Does the Power Go? Power Delivery Computation Memory Cooling (AC) 10 MW 10 MW 4.7 MW 3 MW 2 MW 2 MW 1 MW 1 MW Storage 0.3 MW 0.3 MW Courtesy: P. Franzon, NCSU 33% 47% 30% EEM216A / Fall 2008 D. Markovic / Slide 6 It is not just Computation 40% - 50% lost just in power delivery! Source: Intel Courtesy: P. Franzon, NCSU
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EEM216A / Fall 2008 D. Markovic / Slide 7 Memories ± DDR2 energy budget Total energy/access ~ 550 pJ / bit ± Energy to read a DRAM cell ~ 30 fJ ± Efficiency = 1/20,000 i.e. 0.005% Courtesy: P. Franzon, NCSU EEM216A / Fall 2008 D. Markovic / Slide 8 Computation ± FP Multiply in 45 nm technology: 45 pJ/FLOP ± pJ/cycle in a 45 nm RISC processor 1500 pJ/cycle ± Computation is 3% efficient (at best – ignores “overhead” instructions) Courtesy: P. Franzon, NCSU
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EEM216A / Fall 2008 D. Markovic / Slide 9 Putting it All Together ± For every 1 MJ of energy going into a data center 15 kJ goes into core computation (1.5%) 5 J goes into accessing memory cells ± The rest is “wasted” 3% × 1/3 (delivery and cooling) × 1/2 (distribution) = 0.5% of the total power is used for computations! ± On current scaling trends, a 1000 PetaFlop machine would require 80 MW of power just for the computer 240 MW of total power (including delivery) Courtesy: P. Franzon, NCSU EEM216A / Fall 2008 D. Markovic / Slide 10 1. Power consumption in CMOS 2. Balancing leakage power 3. Power and performance are tightly coupled and have to be jointly optimized 4. Principles of power minimization Outline
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EEM216A / Fall 2008 D. Markovic / Slide 11 Where does power go in CMOS? ± Switching power Charging capacitors ± Leakage power Transistors are imperfect switches ± Short-circuit power Both pull-up & pull-down on during transition ± Static currents Biasing currents 1. Know Your Enemy EEM216A / Fall 2008 D. Markovic / Slide 12 ± One half of the power from the supply is consumed in the pull-up network and one half is stored on C L ± Charge from C L is dumped during the 1 0 transition V dd V out
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M216A_1_Lec-07-Dynamic-Power-n2 - EEM216A Fall 2008 Lecture...

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