M216A_1_Lec-05-Logical-Effort-n2

# M216A_1_Lec-05-Logical-Effort-n2 - EEM216A Fall 2008...

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Logical Effort EEM216A – Fall 2008 Lecture 5 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 Concept of Logical Effort ± Instead of running lots of simulations Simplified: (almost) back-of-envelope calculations of delay ± Basic concept: Delay = R gate (C load + C self ) = R gate C load + R gate C self Logical Effort basic equation: d = f + p d is the delay (normalized) f is known as the effort delay p is known as the parasitic delay d = Delay/ τ = (R gate C load + R gate C self ) / R 0 C 0 Normalized to the delay of a FO-1 inverter (no self load) With R 0 = R gate , d = fanout + normalized parasitic So f is essentially equivalent to fanout d is a measure that is independent of process, voltage, temp

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EEM216A / Fall 2008 D. Markovic / Slide 3 The Logical Effort Way of Thinking… ± Gate delay we used up to now: ± Another way to write this formula is: EEM216A / Fall 2008 D. Markovic / Slide 4 Now Normalize the Delay Strategy: normalize to the time constant of an inverter ± Approach 1: normalize to fictitious “technology time constant” ± Approach 2: normalize to the intrinsic delay of an inverter Both formulations exist in the literature We use approach 1 from the original logical theory Doesn’t really matter – it’s just a constant
EEM216A / Fall 2008 D. Markovic / Slide 5 Normalized Delay Strategy: normalize to the time constant of an inverter ± Approach 1: normalize to fictitious “technology time constant” ± Normalized delay: ± Even simpler: Logical effort terms ± Logical effort (g) Electrical fanout (h) Parasitic delay (p) EEM216A / Fall 2008 D. Markovic / Slide 6 The Meaning of Logical Effort Terms Logical effort terms ± Logical effort (g) Electrical fanout (h) Parasitic delay (p) Intuition ± Logical effort (g) R on ratio for equal C in C in ratio for equal R on ± Electrical fanout (h) C out / C in ratio (gate cap only, diffusion counts in the p term) ± Parasitic delay (p) Ratio of parasitic capacitances for equal R on

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EEM216A / Fall 2008 D. Markovic / Slide 7 Calibrating the Model ± The values for g and p can be extracted from simulation Because, d = g · h + p Simulating the delay of the gate for different loads Drive itself with different multiplication factor Extract τ using inverter with no self-loading (AS, AD, PS, PD = 0) Vary the inputs (and rise/fall) for different g and p Delay/ τ C load / C in Gate Slope is g Intercept is p EEM216A / Fall 2008 D. Markovic / Slide 8 Logical and Electrical Effort ± Instead of just d = f + p, let f = g · h g = logical effort (of a gate) Cost of implementing logic h = electrical effort Cost of driving a load ± f= R gate C load /R 0 C 0 , p = R gate C self /R 0 C 0 Let R 0 = R inv where R inv = R gate , C 0 = C inv p = C self / C inv , f = C in C load / C in C inv C in is the gate’s input capacitance (for the particular input) g = C in / C inv Each gate (and each input of every gate) has different values h = C load / C in Output to input capacitance ratio
EEM216A / Fall 2008 D. Markovic / Slide 9 1 2 3 4 5 6 12345 parasitic delay effort delay Electrical effort: h = C

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## M216A_1_Lec-05-Logical-Effort-n2 - EEM216A Fall 2008...

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