M216A_1_Lec-04-Speed-Optimization-n2

# M216A_1_Lec-04-Speed-Optimization-n2 - EEM216A Fall 2008...

This preview shows pages 1–6. Sign up to view the full content.

Optimization for Speed EEM216A – Fall 2008 Lecture 4 Dejan Markovic [email protected] EEM216A / Fall 2008 D. Markovic / Slide 2 Speed Optimization via Gate Sizing ± Gate sizing basics P:N ratio Complex gates Velocity saturation Tapering ± Developing intuition Number of stages vs. fanout Popular inverter chain example ± Formal approach: logical effort ± Sizing optimization for speed

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
EEM216A / Fall 2008 D. Markovic / Slide 3 Basic Gate Sizing Relationships ± Rise and fall delays are determined by the pull-up and pull-down “strength” Besides the dimensions, strength depends on µ , C OX , V T PMOS is weaker because of lower µ P Larger P network than N network ± Increasing size of gate can reduce delay Inverse (1/W) relationship with resistance (and hence delay) BUT it can slow down the gate driving it Proportional (W) relationship with Capacitance. So be careful! EEM216A / Fall 2008 D. Markovic / Slide 4 P:N Ratio for “Equal” Rise and Fall Delay ± Good to have roughly equal delays for different transitions Don’t need to worry about a worst-case sequence Size P’s to compensate for mobility C OX , V T , L are roughly the same. Make the Pull-up and Pull-down resistances equal R N /R P = 1 = µ P W P / µ N W N = k β, k = mobility ratio, β = P:N ratio W P /W N = µ N / µ P ± Approximately the same as making V THL = V DD /2 ± Easy for an inverter What about more complex gates? W I R DRV µ / 1 / 1
EEM216A / Fall 2008 D. Markovic / Slide 5 Complex Gate Sizing ± N-stack series devices need N times lower resistance N × Width ± Make worst case strength of each path equal Multi-input transition can result in stronger network ± Long series stacking is VERY bad C W W W W 2W 2W B A C W W 6W 6W B A W 6W Ex: β =2 EEM216A / Fall 2008 D. Markovic / Slide 6 Accounting for Velocity Saturation ± Series stacking is actually less velocity saturated If we use R no_stack = (4/3)R stack Adjust the single device size to account for velocity saturation C W W W W 2W 2W B A C W W 6W 6W B A W 6W Ex: β =2 4W/3 4W/3

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
EEM216A / Fall 2008 D. Markovic / Slide 7 P:N Ratio for Minimum Delay ± Delay of an inverter chain (2 inverters) to include t pLH & t pHL ± Let R PDRV ~ R O ’/W P µ P , R NDRV ~ R O ’/W N µ N , C G ~ C O (1+W P /W N ) ± t PD = t D1 + t D2 = R O ’(1/W P µ P + 1/W N µ N ) C O (1+W P /W N ) ± τ N (1+1/k β )(1+ β ) ± Min(t PD ): dt PD /d β = 0 = τ N (1-k/ β 2 ) ± So β = W P /W N = sqrt( µ N / µ P ) Intuition is that since NMOS has more drive for a given size, it is better to use more NMOS W P W P W N W N in out W P W N EEM216A / Fall 2008 D. Markovic / Slide 8 Plot of P:N Ratio to Delay ± Normalized Delay to that of an Inverter driving another inverter with 4x the size (fanout of 4) Where µ = mobility ratio, and β is P:N ratio Curve is relatively flat so not a strong delay tradeoff β FO4 inverter delay ( τ )
EEM216A / Fall 2008 D. Markovic / Slide 9 Tapering ± One observation from Elmore delay is that capacitance closer to the v-source has less effect on delay τ delay = R 1 (C 1 )+(R 1 +R 2 )(C 2 ) C 1

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 25

M216A_1_Lec-04-Speed-Optimization-n2 - EEM216A Fall 2008...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online