M216A_1_Lec-03-Delay-Models-n2

M216A_1_Lec-03-Delay-Models-n2 - EEM216A Fall 2008 Lecture...

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Delay Models EEM216A – Fall 2008 Lecture 3 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 Gate Delay ± Gate delay is a measure of time between an input transition and an output transition May have different delays for different input to output paths Different for an upward or downward transition t pLH – propagation delay from LOW-to-HIGH (of the output) ± A transition is defined as the time at which a signal crosses a logical threshold voltage Digital abstraction for 1 and 0 Often use V DD /2 Logic Gates Inputs Outputs
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EEM216A / Fall 2008 D. Markovic / Slide 3 Static CMOS Gate Delay ± Output of a gate drives the inputs to other gates (and wires) Only pull-up or pull-down, not both Capacitive loads V M t pHL in out out in in t PD1 t PD2 out t PD = t PD1 + t PD2 C LOAD ± The delay of EACH stage is treated as a separately calculable element ± Transition moment is defined at V M (logical threshold) EEM216A / Fall 2008 D. Markovic / Slide 4 Voltage Transfer Characteristics (VTC) ± Characterize the DC response of a simple inverter ± 5 Regions of operation V in <V TN , V out =V DD , N-Off, P-Lin V in >V TN , V out >V in -V TP N-Sat, P-Lin V in >V TN , V in -V TP >V out >V in -V TN N-Sat, P-Sat V in <V DD +V TP , V in -V TN >V out N-Lin, P-Sat V in > V DD +V TP , V out =V GND , N-Lin, P-Off ± Logical threshold When V in = V out in out W N /L N W P /L P V in V out P:Lin N:Off P:Lin N:Sat P:Sat N:Sat P:Sat N:Lin P:Off N:Lin V M
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EEM216A / Fall 2008 D. Markovic / Slide 5 Logical Threshold Voltage ± Set I DSATP = I DSATN and solve Dependence on P:N sizing and mobility ratio Slight dependence on V TP/N ± Not so easy if not an inverter Depends on which input the gate is driving In 1 to Out transfer characteristic can be different from In 2 to Out Use V DD /2 as average case Unless severely skew the P:N ratio V in V out V M in out W N /L N W P /L P in 1 out W N1 W P1 in 1 W N2 W P2 in 2 in 2 EEM216A / Fall 2008 D. Markovic / Slide 6 0 2 2 = + DSATp Tp DD M DSATp p DSATn Tn M DSATn n V V V V V k V V V V k Calculating V M 10 0 10 1 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M V(V) W p /W n High V DD : r V V V r V V V DSATp Tp DD DSATn Tn M + + + + + = 1 2 2 n satn p satp DSATn n DSATp p W W V k V k r = = υ Long L or low V DD :
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EEM216A / Fall 2008 D. Markovic / Slide 7 Sensitivity of VTC to P:N ± Fortunately, the logical threshold is not very sensitive to P:N ratio Ranges from 1.35V to 1.75V (from a 3.3V V DD ) V DD /2 is quite reasonable EEM216A / Fall 2008 D. Markovic / Slide 8 V out t f t pHL t pLH t r t V in t 90% 10% 50% 50% 2 pHL pLH p t t t + = Delay Definitions
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EEM216A / Fall 2008 D. Markovic / Slide 9 RC Model ± We can use the resistor model of a transistor Take into account the different regions of operation Use a realistic transition time to model an input switching ± We can take the average capacitance of a transistor as well ± The easy model
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M216A_1_Lec-03-Delay-Models-n2 - EEM216A Fall 2008 Lecture...

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