This preview shows pages 1–7. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: Scaling, MOS Transistor Models EEM216A Fall 2008 Lecture 2 Dejan Markovic dejan@ee.ucla.edu EEM216A / Fall 2008 D. Markovic / Slide 2 Announcements Homework #1 will be posted by 9pm tonight Due Wed, Oct 8, 2pm (in class or 56127CC) Your classwiki accounts (216a group) have been activated 30 students have signed up so far (~20 missing) Please spread the word around (for those who didnt come to class & didnt put their email on the class mailing list on EEweb) MSOL: check your email for important announcements (EE account, classwiki, discussions, office hours) Todays lecture Technology scaling MOS transistor modeling EEM216A / Fall 2008 D. Markovic / Slide 3 Technology Scaling is Power Driven 1970 1985 2000 Bipolar NMOS CMOS ??? power wall power wall power wall System performance has benefited from higher integration In the mid 80s, CMOS displaced NMOS technologies to address power dissipation CMOS delivered better cost performance since it was more energy efficient and improved the integration level At that time CMOS was on the horizon Replacing CMOS by another more energy efficient technology is a distant prospect now Lowpower highspeed CMOS technology is becoming an indispensable, rather than desirable, technology Power is the main challenge we need to address EEM216A / Fall 2008 D. Markovic / Slide 4 The Limits Theoretical Practical System Circuit Device Material Fundamental [J. Meindl, Proc. IEEE, 1995] Theoretical limits: physics Practical limits: + manufacturing cost EEM216A / Fall 2008 D. Markovic / Slide 5 Circuit Limits #1: logic levels (gain) #2: energy/transition #3: delay #4: global interconnect EEM216A / Fall 2008 D. Markovic / Slide 6 Circuit Limit #1: Logic Levels (Gain) Distinguish logic 0s from 1s (restore logic levels gain >1) [J. Meindl, Proc. IEEE, 1995] EEM216A / Fall 2008 D. Markovic / Slide 7 Circuit Limits (Cont.) #2: energy/transition Neglecting static current #3: delay Limited by #4: global interconnect Interconnect delay should not exceed gate delay EEM216A / Fall 2008 D. Markovic / Slide 8 Practical Limits Scaling towards fundamental limits [J. Meindl, Proc. IEEE, 1995] ~130nm is the most cost effective technology (the last generation for which deep UV microlithography will suffice) EEM216A / Fall 2008 D. Markovic / Slide 9 Practical Limits (Cont.) Metric: chip size [J. Meindl, Proc. IEEE, 1995] D = 50mm (16 wafer) D = 40mm (12 wafer) D = 25mm (8 wafer) EEM216A / Fall 2008 D. Markovic / Slide 10 Practical Limits (Cont.) Packing efficiency = # transistors / min feature area [J. Meindl, Proc. IEEE, 1995] 3D / vertical integration Layout density # mask levels EEM216A / Fall 2008 D. Markovic / Slide 11 D. Markovic / Slide 11 Basic Scaling Trends Pentium Pro Pentium 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 1000 10000 1970 1980 1990 2000 2010...
View
Full
Document
This note was uploaded on 02/06/2011 for the course EE M216A taught by Professor Marković during the Spring '08 term at UCLA.
 Spring '08
 Marković
 Transistor

Click to edit the document details