06 Flip-flops - EE2000 Logic Circuit Design 6 Flip-Flops 1...

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1 EE2000 Logic Circuit Design 6 Flip-Flops ±±±±±
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2 Introduction ± Two classes of logic circuits ± Combinational logic circuits ± Sequential circuits ± Up to now, studied only combinational logic circuits ± Outputs depend only on what the inputs are present at the moment ± Sequential circuits ± Outputs depend not only on present inputs, but also on past history (sequence) of inputs ± Therefore, past history of inputs must be preserved ± Seq. circuits are said to have memory
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3 Sequential Circuit Example ± A circuit with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times ± Input x is not fixed, but changing from time to time ± Input sequence x : 01001100101000111… ± The circuit must store the last three inputs of x in order produce correct output z ± Require memory to store that information ± The information is called the state of the circuit x z Input ? output memory
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4 Modulo Counter ± Memory to store the current counting no. ? memory
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5 Traffic Light Circuit ± Memory to store the current state State A State B State C State D
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6 Vending Machine ± There are memory elements to store the current state ± There are many information ± Deposited money ± Selected drink ± Change amount ± etc ± How to represent the states? ± Not this chapter, but next notes ? Clock $6.0 $6.0 $6.0 $6.0 . Ze ro Col a Max Up memory
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7 Memory ± Storage element to store state of the circuit ± Basic logic elements provide memory ± Latches ± Flip-flops ± This lecture note focuses on the structure and operation of several types of latches and flip-flops
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8 Outline ± 6.1 Latches ± Buffer ± SR , S’R’ , and D Latches ± Gated Latches ± 6.2 Flip-Flops ± Master-Slave Flip-Flops ± Edge-Triggered Flip-Flops ± SR , D , JK and T Flip-flops ± Synchronous and Asynchronous Inputs
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9 6.1 Latches
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10 6.1.1 Storage Element: Buffer ± Symbol ± How to store a value? ± Connect the output of the buffer to its input ± Information stored for indefinite time (as long as power is applied) gate delay = t G t G t G 0 0 1 1 x (x’)’ = x Can be implemented simply using 2 inverters
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11 Important Concept: Gate Delay The value of gate outputs is not updated at the same time ? ? ? ? 0 ? ? ? 0 ? 1 ? 0 0 1 0 At time = 0, Set x = 0 At time = t G At time = 2 t G At time = 3 t G Initial values are unknown
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12 Buffer x x x x x Q’ Q Obviously, Q = x’ and Q’ = x x x Q’ Q Q Q’ Q Q’
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Basic Bistable Element ± The output of the first gate serving as the input to the second gate, and ± The output of the second gate serving as the input to the first gate ± This cross-coupled circuit have two stable states ± Called bistable element ± The previous implementation can only store information, but no way to change the value! ± Use
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This note was uploaded on 02/06/2011 for the course EE 2000 taught by Professor Vancwting during the Spring '07 term at City University of Hong Kong.

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06 Flip-flops - EE2000 Logic Circuit Design 6 Flip-Flops 1...

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