07 Sequential Logic Circuit Design

07 Sequential Logic Circuit Design - EE2000 Logic Circuit...

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1 EE2000 Logic Circuit Design 7 Sequential Logic Circuit Design ±±±±±
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2 Example (Revisit) ± A circuit with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times ± Input x is not fixed, but changing from time to time ± Input sequence x : 01001100101000111… ± The circuit must remember the last three inputs of x in order produce correct output z ± This circuit is called sequence recognizer x z Input ? output memory
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3 Sequence Recognizer ± A circuit that recognizes the occurrence of a particular sequence of bits ± One input X and one output Z ± The circuit recognize the occurrence of the sequence of input bits “111” on X ± If past two inputs to the circuit were “11” and current input is a “1”, Z equal to 1 ± Otherwise, Z equal to 0 ± Input sequence X : 01011001000 111 ± Output sequence Z : 0000000000000 1
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4 Requirements ± Require a combinational circuit ( A ) to determine the output ± If the current input is 0, output must be 0 ± If the current input is 1, what will be the output? Depends on the previous two inputs! ± Require memories ( B ) to remember the history of input sequence ± e.g. what are the previous two inputs? ± Output 1 if previous two inputs were “11” (and current input is 1), output 0 if previous inputs were not “11” ± Require a combination circuit ( C ) to “update” the input history
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5 Sequential Circuit Structure Input X Output Z Present states Q i A C B B
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6 Long Sequence Recognizer ± How to recognize the occurrence of a long sequence of input bits “11010101100110”? ± This match sequence is 14 bits long ± Need 13 flip-flops to remember the previous 13 inputs ± Not a good design ± Remember the state instead of memorizing the previous input sequence!
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7 Outline ± 7.1 Finite State Machines ± Concept of States ± Mealy Machines ± Moore Machines ± Excitation Tables ± 7.2 Design of Sequential Logic Circuits ± Design Procedure ± Sequence Recognizer ± Modulo- n Counter
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8 7.1 Finite State Machines
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9 7.1.1 Concept of States ± Due to the repeatness of the inputs, the input can be group into classes ± These classes summarize the effect of past inputs on present and future outputs ± The classes are known as states ± Represented by auxiliary variables S i ± The number of states are usually finite ± Two state machines: Mealy machine, and Moore machine
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10 7.1.2 Mealy Machine ± A state is represented by a circle ± Transitions between states are indicated by directed lines connecting the circles S i S i S j S j X / Z State S i S i S i For the present state S i , if the next input is x , the state will change to S j and produce an output z
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Mealy Machine Example ± What is the meaning of this stage diagram ? S
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07 Sequential Logic Circuit Design - EE2000 Logic Circuit...

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