07S Sequential Logic Circuit Design

# 07S Sequential Logic Circuit Design - EE2000 Logic Circuit...

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1 EE2000 Logic Circuit Design 7 Sequential Logic Circuit Design (Supplementary Notes) ±±±±±

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2 Advanced Example 1 Free-running Counter
3 Example: Counter ± Specification ± Design a free-running counter with counting sequence 2, 4, 5, 3, 7, 2, …(and repeat) using D flip-flops ± Comment if it is self started counter ± What is a self started counter? ± The initial value of flip-flips is unknown ± So the initial state of your circuit is unknown ± Necessary to ensure that the circuit eventually goes into one of the valid states so it can resume normal operation automatically ± Otherwise, if the sequential circuit circulates among invalid states, there will be no way to bring it back to its intended sequence of state transitions ± A careful designer must ensure that this situation never occurs

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4 Example: Counter ± Analysis ± Free-running 0 inputs ± There are five numbers: 2, 4, 5, 3, 7 ± Therefore, there are 5 states ± 3 flip-flops are required ± The largest number is 7 = (111) 2 ± Therefore, the number of outputs is 3 ± The counter will count ± 010 100 101 011 111 010 …
5 Moore Machine Structure (no inputs) Outputs Present states Q i A C B B Z 0 Z 1 Z 2 B

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6 Example: Counter ± Formulation ± Derive the state diagram and state table S C /101 S C /101 S A /010 S A /010 S B /100 S B /100 S D /011 S D /011 PS NS Output Z 0 Z 1 Z 2 S A S B 0 1 0 S B S C 1 0 0 S C S D 1 0 1 S D S E 0 1 1 S E S A 1 1 1 S E /111 S E /111
7 Example: Counter ± Assign the state as the output code ± S A = 010, S B = 100, S C = 101, S D = 011, S E = 111 ± Rewrite the state table as follow PS NS Output Q A Q B Q C Q A Q B Q C Z 0 Z 1 Z 2 0 0 0 x x x x x x 0 0 1 x x x x x x 0 1 0 1 0 0 0 1 0 0 1 1 1 1 1 0 1 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 x x x x x x 1 1 1 0 1 0 1 1 1 PS NS Output Z 0 Z 1 Z 2 S A S B 0 1 0 S B S C 1 0 0 S C S D 1 0 1 S D S E 0 1 1 S E S A 1 1 1

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## This note was uploaded on 02/06/2011 for the course EE 2000 taught by Professor Vancwting during the Spring '07 term at City University of Hong Kong.

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07S Sequential Logic Circuit Design - EE2000 Logic Circuit...

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