08 Simplification of Sequential Circuits

08 Simplification of Sequential Circuits - 1 EE2000 Logic...

Info iconThis preview shows pages 1–12. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 EE2000 Logic Circuit Design 8 Simplification of Sequential Circuits ¡ ¡ ¡ ¡ 2 Combination vs. Sequential ¡ In designing combination logic circuits, ¡ Read the specification ¡ Derive the truth table ¡ Minimize the output functions by ¡ Boolean algebra, K-map, or Q-M method ¡ In designing sequential logic circuits, ¡ Read the specification ¡ Derive the state diagram and state table ¡ Minimize the state table (how?) 3 Outline ¡ 8.1 Redundant State Elimination ¡ 8.1.1 Inspection ¡ 8.1.2 Partitioning ¡ 8.1.3 Implication Table ¡ 8.2 Sequential Circuit Analysis ¡ 8.3 Design with Programmable Logic Device 4 8.1 Redundant State Elimination 5 Redundant State Elimination ¡ For combination logic circuits, minimizing the output functions means ¡ Reducing the number of logic gates ¡ i.e. reducing the cost and also space of the circuit ¡ For sequential logic circuits, minimizing the state table means ¡ Reducing the redundant states ¡ i.e. reducing the number of flip-flops ¡ Reducing the cost and space ¡ Also, if too many flip-flops, require Q-M to simplify the output functions and flip-flip input functions 6 Concept of Equivalent States ¡ Are these two state diagram equivalent? S C S C 1/0 S A S A S B S B 1/1 1/1 0/1 0/0 0/0 S D S D 0/1 1/1 1/0 S A S A S B S B 1/1 0/1 0/0 S D S D 0/1 1/1 S C S C 7 Concept of Equivalent States ¡ Compare their state table Present State (PS) Input X 1 S A S B / 1 S C / 0 S B S D / 0 S A / 1 S C S D / 0 S A / 1 S D S D / 1 S A / 1 Present State (PS) Input X 1 S A S B / 1 S C / 0 S B S C S D / 0 S D / 0 S A / 1 S A / 1 S D S D / 1 S A / 1 S C S C 1/0 S A S A S B S B 1/1 1/1 0/1 0/0 0/0 S D S D 0/1 1/1 1/0 S A S A S B S B 1/1 0/1 0/0 S D S D 0/1 1/1 S C S C S B 8 Concept of Equivalent States ¡ If there are two states that given the same input conditions ¡ their outputs are the same, AND ¡ their corresponding next state are also the same ¡ They are called equivalent states ¡ Or in short, ¡ States that have the same next states AND outputs are equivalent ¡ i.e. one of the states is redundant and can be eliminated 9 8.1.1. Inspection ¡ An example state diagram has been shown on the right hand side ¡ How many flip-flops required to implement this sequential circuit? ¡ Since 15 states, require 4 flip-flops (why?) S A S A S B S B S D S D S E S E S H S H S I S I S J S J S K S K S C S C S F S F S G S G S L S L S M S M S N S N S P S P 0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/1 0/0 1/0 0/0 1/1 0/0 1/0 0/0 1/0 0/0 1/0 10 State Diagram → Table ¡ Derive the state table from the state diagram Present State (PS) Input X 1 S A S B / 0 S C / 0 S B S D / 0 S E / 0 S C S F / 0 S G / 0 S D S H / 0 S I / 0 S E S J / 0 S K / 0 S F S L / 0 S M / 0 S G S N / 0 S P / 0 S H S A / 0 S B / 0 S I S A / 0 S B / 0 S J S A / 0 S A / 1 S K S A / 0 S B / 0 S L S A / 0 S A / 1 S M S A / 0 S B / 0 S N S A / 0 S B / 0 S P S A / 0 S B / 0 11 Step 1) Find Equivalent States Present State (PS) Input...
View Full Document

This note was uploaded on 02/06/2011 for the course EE 2000 taught by Professor Vancwting during the Spring '07 term at City University of Hong Kong.

Page1 / 73

08 Simplification of Sequential Circuits - 1 EE2000 Logic...

This preview shows document pages 1 - 12. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online