09 Sequencial Functional Blocks

09 Sequencial Functional Blocks - EE2000 Logic Circuit...

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1 EE2000 Logic Circuit Design 9 Sequential Functional Blocks ±±±±
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2 Introduction ± We studied the concept of functional blocks in combinational logic circuit ± Used to construct larger circuit ± e.g. adders, subtractors, comparators, decoders, encoders, multiplexers, demultiplexers, etc ± How about functional blocks in sequential logic circuits? ± Sequential functional blocks ± e.g. registers and counters
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3 Why Functional Blocks? ± Designing logic circuit is tedious ± Combinational logic circuit: ± Truth table minimized output functions circuit diagram ± Sequential logic circuit: ± State diagram minimized state table minimized flip-flop input equations and output functions circuit diagram ± Build circuits that is structural for easier expansion ± e.g. one-bit full adder n -bit full adder ± 1-to-2-line MUX n -to-2 n -line MUX ± How about registers and counters ?
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4 Outline ± 9.1 Registers ± 9.1.1 Registers ± Parallel load, Bidirectional shift ± 9.1.2 Applications ± Serial Data to Parallel Data (and vice versa) ± Serial Adder, accumulator ± 9.2 Counters ± 9.2.1 Asynchronous Counters ± Ripple counters ± 9.2.2 Synchronous Counters ± Up-down counters, modulo counters, ring counters
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5 9.1.1 Registers
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6 Registers ± Memory used for storing (binary) information during the processing of data ± To store n -bit data, require n flip-flips ± n -bit register ± Composed of a set of n edge-triggered flip-flops ± The clock pulse is the enable signal ± Data will be latched to the flip-flops during the clock active period (pos. edge or neg. edge) ± Two designs ± Parallel, or Serial
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7 4-bit Register C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR Clk Parallel data input ( PI ) D 3 D 2 D 1 D 0 Parallel data output ( PO ) Q 3 Q 2 Q 1 Q 0 Note: PRE’ & CLR’ inputs are not drawn in this diagram
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8 Example C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR D 3 D 2 D 1 D 0 Q 3 Q 2 Q 1 Q 0 Note: PRE’ & CLR’ inputs are not drawn in this diagram 1 0 1 1 ? ? ? ? ? ? ? ?
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9 Example C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR D 3 D 2 D 1 D 0 Note: PRE’ & CLR’ inputs are not drawn in this diagram 1 0 1 1 Clk = 1 0 1 1 Q 3 Q 2 Q 1 Q 0 ? ? ? ?
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10 Example C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR Q 3 Q 2 Q 1 Q 0 Note: PRE’ & CLR’ inputs are not drawn in this diagram 1 0 1 1 1 0 1 1 D 3 D 2 D 1 D 0 1 0 1 1 = D 3 = D 2 = D 1 = D 0 After the clock transition
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4-bit Register ± As see from last page, constructed from 4 D - type positive-edge-triggered flip-flops ± The register loads all four D inputs into the flip- flops in parallel (at the positive clock transition) ± Advantage of this design ± Simple, just group the flip-flops together ± Not require any external logic gates ± Disadvantage? ± No enabling!
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This note was uploaded on 02/06/2011 for the course EE 2000 taught by Professor Vancwting during the Spring '07 term at City University of Hong Kong.

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09 Sequencial Functional Blocks - EE2000 Logic Circuit...

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