10 Logic Families - EE2000 Logic Circuit Design 10 Logic...

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1 EE2000 Logic Circuit Design 10 Logic Families ±±±
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2 An Ideal Inverter V in Time GND V CC V out Time GND V CC Input to the inverter Output of the inverter
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3 Non-Ideal Inverter V in Time GND V CC V out Time GND V CC Input to the inverter Output of the inverter
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4 Non-Ideal Inverter V in Time GND V CC V out Time GND V CC Input to the inverter Output of the inverter
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5 Outline ± 10.1 Timing Parameters of Flip-flips ± Propagation delay, output transition time, minimum pulse width, setup time, hold time ± 10.2 Electrical Characteristics of Logic Gates ± Logic levels, noise margins, speed of operation, power dissipation, operation temperature, fan-in, fan-out
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6 10.1 Timing Parameters of Flip-flops
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7 Timing Considerations ± Function tables of latches / flip-flops specify the state outputs ± However responses to the inputs are not really immediate (occur after some time delay) ± In order to achieve the desired responses, certain time constraints must be satisfied ± Five timing parameters are considered
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8 Five Timing Parameters ± 1. Propagation delay ± 2. Output transition time ± 3. Minimum pulse width ± 4. Setup time ± 5. Hold time Clk D Q ? Timing diagram of a positive edge-triggered D FF Clk D Q ?
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9 10.1.1 Propagation Delay ± The amount of time it takes for the output of FF to change its state from a clock trigger (or asynchronous preset or clear) ± Denoted by t pHL and t pLH ± t pHL : P ropagation time from a H IGH to a L OW ± t pLH : P ropagation time from a L OW to a H IGH ± Defined from the 50% point of the input pulse to the 50% point of the output pulse
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10 Example: t pHL and t pLH ± Illustrate the propagation delays in an SR latch using timing diagram S Q Q’ R t pHL t pLH t pHL t pLH Time Assume the initial value of Q and Q’ are (0, 1) 50% point of the input/output pulse
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11 10.1.2 Output Transition Time ± The rise time or fall time of the output ± Denoted by t tHL and t tLH ± t tLH : 10% to 90% time, or L OW to H IGH t ransition time ± t tHL : 90% to 10% time, or H IGH to L OW t ransition time
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12 Example: t tHL and t tLH ± Illustrate the output transition time in an SR latch using timing diagram S Q Q’ R t tHL t tLH t tHL t tLH Time HIGH to LOW transition time LOW to HIGH transition time
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13 10.1.3 Minimum Pulse Width ± The minimum amount of time that the input signal must be applied in order to produce a correct result ± To insure the device has enough time to capture and response to the input values correctly ± Pulse width is denoted by t w ± Minimum pulse width is denoted by t w(min)
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10 Logic Families - EE2000 Logic Circuit Design 10 Logic...

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