This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: CITY UNIVERSITY OF HONG KONG Course code & title : EE20200 Logic Circuit Design
Session : Semester B 20002001
Time allowed : Two hours This paper has 8 pages. (including this page) 1. This paper consists of 8 questions in 2 sections. 2. Answer ALL questions in Section A. And choose TWQ questions from Section B. 3. Use a new page for each question. P 1 Section A (50 %)
Attempt ALL questions from this Section. Q1. Simplify the following expression using the Quine—McCluskey tabular minimization
method: f(A,B,C,D)=ABCD+ZECD+ZBEB+ABEB+AEED+A§CD+ABCD (8 marks) Q2. (a) Use the Hamming code (with odd parity including the parity bit itself) to
encode the 4bit messages 1001. (b) For the Hamming code used in part (a), decode the received bits 111 1000. (8 marks) Q3. Mr. Bean has designed a logic gate whose truth table is shown in Table Q3. He .
claims that his gate has the universal property. Verify his claim. Table Q3
(8 marks) Q4. For the synchronous sequential circuit shown in Figure Q4, complete the timing
diagram shown in Appendix A. The initial state of Q is low. (8 marks) Figure Q4 P2 Q5. P3 A serial communication system synchronizes with a sync word 0110. (a) Design a state diagram for a sequence detection circuit, which produces an
output Z. Z is set to high when the sync word is detected. For example, X=10011000110110001000
Z=00000100001001000000 (b) With the minimum number of states, derive the logic equations to implement
the detection circuit using Tﬂip ﬂops. Draw your circuit. (18 marks) ﬁegtign B (50 %) (Choose two question to answer25 marks for each question) Q6. P4 (3) Using Dﬂipﬂops, 4to1 multiplexers, and NAND gates, design a 4bit shift
register module that has following function table: Mode
__ Shift riht all 4bit
__ Shift left all 4bit __ S nchronous clear
Johnson counter (12 marks) (b) Use AND gates, OR gates, and Inverters to design a level trigger latch whose
truth table is shown below. Draw your design. Asynchronus Enable Preseth state Input New state clear Q* CLEAR (7 marks) (c) Use two latches designed in part(b) and some inverters to construct a positive
edge trigger ﬂip ﬂop whose state diagram is shown below. Draw your design. Asynchronous Input Clock Output
clear CLK
CLEAR (6 marks) Q7. P5 (3) (b) (d) Given three 2—tol multiplexers, build a 4—to—1 multiplexers.
(4 marks) Using 2to4 decoders and NAND gates, implement a 4to1 multiplexers.
(4 marks) Using 4to1 multiplexers only, implement a onebit half adder. Hence, using
half adders only, construct a onebit full adder. Draw your design. (8 marks) Construct a 4bit arithmetic unit, which performs some arithmetic two 4bit binary numbers, A = (a3 , a2 , a1, a0) and B = (b3 , b2 ,b1 , b0) . The 4bit result
and the carry output are denoted as F 2 (f3, f2, f1, f0) and com , respectively.
Hint: build a standard 4bit adder ﬁrst. _
—n_—
—n_
——n (9 marks) Function Q8. P6 (a) Construct a twolevel NAND gate circuit that converts a 4bit l’complement number signed magnitude number to a 4bit 2’s complement number. Decimal vaues 1’s complement 2’s complement
numbers numbers
D3D2D1Do G3GzGlGo “——
__—
__—
“—— H N (8 marks) (b) Use the PLA shown in Appendix B to implement the 1’s complementtoZ’s complement converter mentioned in part (a). (8 marks) (c) Given a 16x4 ROM (it has 16 storage cells and each cell can store four bits
data), explain how to use this ROM to implement the 1’s complementto—Z’s complement converter mentioned in part (a). (4 marks) (d) Given a synchronous circuit shown in Figure Q8, explain how to use this
circuit to implement the 1’s complementtoZ’s complement converter described in part (a). asynchronous reset
Figure Q8 END (5 marks) Appendix A clk P7 Appendix B lllllllllﬁdD 
Illlllllll—ﬁ" 
llllllllll—ﬁ" 
IIIIIIIIII—ﬁ" 
lllllllllHD  D .
IIIIIIIIIP§== . ...
View
Full Document
 Spring '07
 VanCWTing

Click to edit the document details