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Unformatted text preview: CITY UNIVERSITY OF HONG KONG Course code & title : EE202OO Logic Circuit Design
Session : Semester A 2001/02
Time allowed : Two hours This paper has 5 pages (including this cover page). Instructions to candidates:
1. This paper contains TWO parts. 2. Students MUST answer all the questions in Part A. And choose TWO
questions from Part B. Start a NEW page for EACH QUESTION. U) PART A (Answer all questions in this part  total of 50 marks) 1. b) 6. Calculate 110001 — 001110, if the two binary numbers are in 2’s complement
representation. Express the result in decimal value. [5 marks]
Use Boolean algebra to simplify the following switching function: ab2+5bd+ab2+ac([email protected])+5b2d [6 marks] Use 4to1 MUX to design a circuit with positive logic output to perform the following
Boolean function: f(a,b,c,d) = HM(1,6,7,10,12)+dc(3,4,9,15). Draw the circuit. [9 marks] Design and draw the circuit of a 4input priority encoder.
[9 marks] Use implication table method to ﬁnd the reduced state table for the state table shown in
Figure Q5. NS/output
PS X=0 X=1
A
B
C
D
E
F
G
Figure Q5
[10 marks]
Find the state diagram and the function of this circuit shown in Figure Q6.
[11 marks] Figure Q6 PART B (Choose two questions to answer  25 marks for each question) 7. A 4input priority encoder can be used to monitor the status of 4 alarm sensors, each
indicating various level of hazard. Two such priority encoders are used to monitor the
status of a machine. A logic circuit comprising of these encoders is used to generate
three levels of alarm by monitoring the status of 8 sensors. The operating details of this
circuit logic are given below: i. An amber alarm (AA) will be generated if the sum of the two encoder outputs is
either 1 or 2. ii. An orange alarm (OA) will be generated if the sum of the two encoder outputs is
either 3 or 4. iii. A red alarm (RA) will be generated if the sum of the two encoder outputs is higher
than 4. Note that the amber, orange and red alarms are indicated by a logic I . Sensors Sensors Figure Q7 (a) Tabulate the truth table of Logic Circuit A shown in Figure Q7(a)
[4 marks] (b) Find the Boolean expressions for the three alarms, AA, OA and RA in terms of w,
x, y and z. [5 marks] (c) If a 2bit full adder shown in Figure Q7(b) is used to implement the Logic Circuit
A, ﬁnd the simplest Boolean expressions of AA, OA and RA in terms of the sum
and carry out of the full adder. Draw a circuit to Show all the input and output
connections of Logic Circuit A. [12 marks] (d) Derive the Boolean expression of AA in terms of w, x, y, 2, 0A and RA.
[4 marks] (a) (i) Design and draw the circuit of a 1bit comparator with: S=1 if A < B, E=1 if
A=B, and G=1 if A>B.
[4 marks] (ii) Use two 1bit comparators designed in part (a)(i) to design a 2bit
comparator. Draw the circuit.
[6 marks] (b) Use D FFs to design a 3bit serial shift register that can perform left shift and right shift operations. Draw the circuit.
[8 marks] (c) Use two 4bit synchronous binary counters, as shown in Figure Q8, to design a
BCD counter to count from 00 to 99. Draw the circuit. Note that the clear and load are synchronous inputs.
[7 marks] C23 (222 0100 Syn.dear SynJoad 9. (a) The state table of a sequential circuit is given in Figure Q9(a). Design the circuit using JK FPS and other logic gates. Circuit is not required.
[12 marks] State assignment NS/output
X=0 X=1
D/O C/O 0 0 1 E/O All 0 1 0 F/ 1 B/O O 1 1 A/ 1 F/ 1 1 0 O C/O E/O 1 O 1 B/O D/ 1
Figure Q9(a) (b) A sequential logic circuit with one input and one output is used to stretch the ﬁrst
two bits of a 4bit sequence as follows: Figure Q9(b) The circuit will ignore the third and fourth bits of the input sequence. After every
four bits, the circuit resets. (i) Draw a Mealy machine to describe the behavior of this sequential circuit. [8 marks]
(ii) Obtain a state table for the circuit (minimum of 7 states).
[5 marks] ****** ****** ...
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This note was uploaded on 02/06/2011 for the course EE 2000 taught by Professor Vancwting during the Spring '07 term at City University of Hong Kong.
 Spring '07
 VanCWTing

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