This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: CITY UNIVERSITY OF HONG KONG Course code & title : EE2000 Logic Circuit Design Session : Semester B 2002—2003 Time allowed : Two hours This paper has 9 pages. _____________________.____.________—_——.—————————~— 1. This paper consists of 11 questions in 2 sections. 2. Answer ALL questions in Section A. And choose TWO questions from Section B. 3. Use a new page for each question. P1 Section A (60 %)
Attempt ALL questions from this Section. Q1. Use Kmap to construct a minimal two—level NAND realization for the following
boolean function: f(A, B, C, D) = Zm(6,8,9,10,11,14,15) + d(0). Draw your circuit.
(5 marks) Q2. (a) Use boolean algebra to simplify the following expression in sumof—product form:
f(A,B,C) = AFC + A§C+ ABC+ ABC +A§C (b) Use the result of part(a), to simplify the following expression in productof— sum
form: f(A,B,C)=(A+§+E)(A+§+C)(A+B+C)(A+B+E)(K+§+C) (7 marks) Q3. The following block of data is received from the transmission system with a vertical
parity system. Horizontal parity is odd; vertical parity is even. 1
0
1
0
1
0
X (a) Find any parity failure.
(b) Correct the error if there is any error. (6 marks) P2 Q4. The truth table of a logic gate is shown in Table Q4. Does this logic gate own the
universal property? Inﬂt A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 Table Q5 (8 marks) Q5. A serial communication system synchronizes with a sync word 0001. Design a state
diagram for a sequence detection circuit to produce an output Z, Z is set to high
when the sync word is detected. For example, X210011000110110001000
Z=00000000100000001000 (8 marks) Q6. A sequential circuit has one JK ﬂip—ﬂop and one T ﬂipﬂop, one input x, and one
output y. The logic diagram of the circuit is shown in Fig. Q7. Derive the state table
and state diagram of the circuit. Figure Q6. (10 marks) P3 Q7. Using Dflip—flops, 4—to1 multiplexers, and basic logic gates, design a 4—bit shift
register module that has following function table: 1 SO Mode
0 Shift right (all 4bit)
l Shift left (all 4—bit)
0 Parallel load
1 i—t‘OOKA All Clear (1 1 marks) Q8. Use the implication table method to obtain the reduced state table for the following
state table. next state/out ut present
state A A/O
B All
C B/l
D D/O
E D/l Table Q8
(5 marks) P4 Section B (40 %)
(Choose two questions to answer20 marks for each question) Q9. P5 Given the following circuit: (a) (b) (c) (d) (6) 55> carry in asynchronous clear
asynchronous set Figure Q9 Construct a half adder based on NOR gates only.
(3 marks) Construct a onebit full adder based on two half adders and some basic logic
gates.
(3 marks) For the circuit shown in Figure Q9, draw its state diagram.
(5 marks) Given a synchronous circuit shown in Figure Q9, explain how to use this circuit to implement the addition of two 4bit binary numbers.
(4 marks) Based on the circuit shown in Figure Q9, use onebit full adder, D—type ﬂip—
flop, and some basic gates to construct a circuit that can carry out the
subtraction of two 4bit binary numbers. Explain the operation of your design. (5 marks) Q10. Given the following state diagram of a counter with E=l counting upward and
E20 stop counting. Figure Q10a (a) Use D—type ﬂip—ﬂops to implement the counter with the state diagram shown in Figure 10a.
(11 marks) (b) Without redesign the counter, describe how to implement the counter in part(a) using T—type ﬂip—ﬂops.
(4 marks) ( c) Suppose each Dtype ﬂip~flop has an asynchronous clear line. Based on the result of part(a), design a circuit with the state diagram shown in Figure 10b. (5 marks) 15:0 5:1
5:0
SO 51
(000) (001) 5:1
W 05:0 52
(011)
E=1 5:1
0% 13:1
SS 54
Q
\_/ 5:0
E=O 5:1
Figure QlOb P6 Q11. Given the following truth table W
1
1
1
O
1
0
O
0 Table Q1 1 (a) Using 3—to—8 decoders and basic gates, implement a logic circuit with the truth
table shown in Table Q11. (4 marks) (b) Use the PLA shown in Appendix A to implement a logic circuit with the truth table shown in Table Q11.
(4 marks) (c) Given an 8x4 ROM (it has 8 storage cells and each cell can store four bits data),
explain how to use this ROM to implement a logic circuit with the truth table shown in Table Q11.
(5 marks) ((1) Use the PAL shown in Appendix B to implement a logic circuit with the truth table shown in Table Q11.
(7 marks) P7 Appendix A  .
O  .
IF  .
 .  .
 .
 . .m
0* ‘ ﬂung—nun". an". an”. B IIIIIIIIIIII X
m IIIIIIIIIII' n
m IIIIIIIIIIIII
A IIIIIIII'III'I ,_ ,_ ,_ ,_ ...
View
Full
Document
 Spring '07
 VanCWTing
 Logic gate, Flipflop, De Morgan's laws

Click to edit the document details