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ee2000 0304

# ee2000 0304 - CITY UNIVERSITY OF HON G KONG Course code&...

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Unformatted text preview: CITY UNIVERSITY OF HON G KONG Course code & title : EE2000 Logic Circuit Design Session : Semester A 2003/04 Time allowed : Two hours M This paper has SEVEN pages (including this cover page). M Instructions to candidates: 1. This paper contains TWO parts. 2. Answer ALL questions in Part A, and TWO questions from Part B. 3. Start a new page for each question. m“ Materials, aids & instruments to be used during examination: Non-programmable portable battery operated calculator h“ PART 1 (Answer ALL questions) Q1. Given an 8-bit number 1001 0011, state the decimal value represented if the number is stored as: (a) unsigned number (b) signed magnitude number (c) 2’s complement number (d) BCD 8421 format. (6 marks) Q2. (a) Use boolean algebra to simplify the following expression in SOP form: f(A,B,C) = A§+ AC+ZE+ EEC (b) Use the results of part(a) to simplify the following expression in POS form: g(a,b,c) = (a+5)(a + exa + 5)(a+5+ c) Hints: (a) Consider the concept of duality; or (b) Let A = (7,3 = b ,C = E and consider the DeMorgan's law. (8 marks) Q3 Given a four variables function: f(a,b,c,d) = Zm(l,7,10,11,13)+ Zd(s,8,15). (a) Find its minimum POS form and draw a NAND gate circuit that implements the function f(a,b,c,d). ‘ (b) Based on the result of part (a), draw a NOR gate circuit that implements a function: g=f(a,b,c,d)- (10 marks) Q4 Table Q4 shows the property of a 2-to-4 decoder module with two active high enable pins. Table Q4 (a) Based on a number of this modules and minimum number of basic gates, construct a 3-to-8 decoder which has one active high enable pin. (b) Describe how to implement a 1-to-8 demultiplexer based on a 3-to-8 decoder with enable input. (9 marks) Q5. Determine a minimal state table for the following Moore machine state table: present state next state input x O 1 A B C 0 B D E 1 C A F 0 D E C l E G H 0 F B H O G D F 1 H F E 0 ' (9 marks) Q6. Find the state table and state diagram for the circuit shown in Figure Q6. Figure Q6 (10 marks) Q7. The signals x and RESET illustrated in Figure Q7b are applied to the circuit given in Figure , Q7a. Complete the timing diagram in Figure Q7b. Figure Q7a Figure Q7b Note: Use the timing waveform Figure Q7b given in Appendix A to answer this question and submit it with your answer book. (8 marks) PART B (Choose any TWO questions) Q8. (3) (b) (C) (d) Q9. (81) (b) (0) Construct a 1-bit full subtracter using TWO 4-to-1 MUXs and basic logic gates. (7 marks) Describe how to use a minimal-size ROM to form a 1-bit full subtracter. State the ROM size (e.g. x-by-y where x is the number of locations of the ROM, and y is the output signals) and show the memory maps the conﬁguration. (5 marks) Cascade FOUR l-bit full subtracters to form a 4-bit ripple subtracter, without any logic gates. (2 marks) Use 4-bit ripple subracters and basic gates to form a 1—digit full BCD subtracter. An algorithm for BCD subtraction is to perform a 4-bit subtraction, and if there is a borrow out, reduce the diﬂerence by six. (6 marks) Consider using ﬂip-ﬂops and basic logic gates to implement a 3-bit counter with the following sequence: 000, 001, 011, 010,110,111,101,100, 000, 001, 011, , . For each ﬂip-ﬂop, ﬁnd the simplest SOP boolean expressions and draw the circuit. (12 marks) Figure Q9 shows a counter with an active high asynchronous preset pin. Its counter sequence is the same as that of part (a). Q2 preset Q1 3-bit counter in part (3) Q0 Figure Q9 Draw a circuit with counting sequence as follow: 000, 001, 011, 010,110,111, 000, 001, 011, ..., ...,. (4 marks) Construct a T-ﬂip-ﬂop with a D-ﬂip-ﬂop and minimum number of basic logic gates. (4 marks) - Q10. (a) A synchronous sequential circuit is used to monitor the scoring of a two-player electronic game. i. Each player will either win or lose in a game and a logic “1” indicates a win and “0” for a loss. ii. A win by a player will offset a win by the other player. iii. Any player with 2 wins ahead of the other player will have a score, and a logic “1” will be generated for output ZA and ZB to indicate a score for Play A and Player B respectively. These 2 wins by the player will then not be counted again. The following listing shows the output of ZA and ZB for various game statuses: A 101110001111 B 010001110000 ZA 000100000101 ZB 000000010000 Draw a single Mealy state machine to describe this sequential circuit. (12 marks) (b) Use the PLA given in Figure Q10 to design the circuit that produces the output F1(A,B,C) and F2(A,B,C) which are deﬁned as: F1(A,B,C) = zm(1,4,7) + Zd.c.(3,5) F2(A,B,C) = Zm(3,5,6) + Zd.c.(4,7) Figure Q10 Note: Use the Figure Q10 given in Appendix A to answer this question and submit it with your answer book. (8 marks) ***** ***** Aggendix A Student ID: . Programme of study: Seat No: Q7: Q10: Figure Q10 ...
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