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Unformatted text preview: CITY UNIVERSITY OF HONG KONG Course code & title : EE20200 Logic Circuit Design
Session : Semester B 199899
Time allowed : Two hours This paper has NINE pages. (Including this page) Answer ALL Questions in Section A and TWO from Section B
SECTION A Q].
Use the Kamaugh Map to prove that A + AB = A + B , [1 marks]
then simplify the folowing equation:
ABC‘D + B(AC + H?) + AB [5 marks] Q2.
Table Q2 shows the truth table ofa logic function. Implement this function by using:
(i) discrete logic gates without simpliﬁcation and [3 marks]
(ii) a 74151A 8input data selector mulitplexer and other logic gates if necessary. [5 marks]
(iii) Compare these two methods. [2 marks] Decimal I I  Inputs _Qutput Digital A3IEA2 A] A0 Y 4 0 1 0 I 0' 3 0
5 0" 1 mB—TTW
__._r.5_... ....0 . 1.._1_._._b_e___1_
—7_'—6": 1 I 1 I 1”“ 1
__8__1__._.0.. 0 . 0. __1._ i; 9 1 0 0 l 0 A3 2
10—i'0‘1‘0‘ Iii—I A“ ‘1)
_i_1__ 1 I 0 0 I 2 Y 1 TTETT' _ z
13 1 1 0 1 1 5
_‘_‘_T1Zf'f1j1.1357.3}: : . . . . .—_ T415114 Table Q2 Figure Q2 Q3. The serial datainput waveform (Data in) and dataselect inputs (So and 81) are sh0wn “in Figure
Q3l. Determine the dataoutput waveforms on Do through D3 for the demultiplexer in Q32. [6 marks] Du
Inpu DD
D]
50 Du:
Sdeu K.”
liar: 0,
it I
[ EC}an
Figure Q3i Figure Q32 Q4.
Referring to Table Q4. and Figure Q4.
(i) Write the canonical expressions of both E and Com by using the inputfoutput characteristics. {5 marks] (ii) Mapping the two expressions of Z and CM and simplify the expressions in SOP terms on
Kamaugh maps. Then implement it with ANDOR logics and inverters.  _ [5 marks]
A=B once... 2'
0 .0 go .0 0
0 0 ' 1 '0 1 0 i 0 '0 1 Input { Sum
"'_—_—" ‘— bits ..__]___._0_ Output can'y
 I 0 .0 0 I ' lnputeany
1 I 0 1 1 '0— Table Q4 Figure Q4 Q5. What are the advantages of an edge triggered ﬂipﬂop over a level triggered device? [4 marks] Q6.
Suppose that HIGH levels are applied to the 2 input and the 9 input of the circuit in Figure Q6. A 0digit input is not needed because the BCD outputs are all LOW when all the inputs are
LOW. (i) What are the states of the output lines?
[3 marks] (ii) Does this represent a valid BCD code?
[1 marks] A0 (L58)
2
3
A:
4
5
6 A
7 2
8
9 A3 {15133) Figure Q6 SECTION B Q7(a). . Fourbit serial BCD messages arrive, most signiﬁcant digit ﬁrst, on terminals X and Y in
Figure Q7(a), bit by bit. Variables x and y are used to denote their magnitude. Each data
bit is synchronized with a clock pulse on terminal c. Design a circuit that generates a pulse on terminal Tl ifx > y, on terminal T3 ifx < y, and
on terminal T2 ifx=y. (i) Draw a state diagram of the fourbit serial BCD messages comparator. [6 marks]
(ii) Obtain the Boolean equations ofthe fourbit serial BCD comparator.
[9 marks]
0
T]
X X
T2
y Y T3 Figure Q?(a) Q7(b).
Design a ﬁre alarm detector with the following terminal characteristics. The appearance of
a ﬁre alarm signalfactivates an alarm bell 6, turns a green light g off and a red light r on.
The operator tunrs off the bell by pressing an ackn0wledge switch a. When the alarm clears
itself, the red light turns off, the green light turns on and the bell is automatically
reactivated to attract the operator's attention. The bell is turned off when the operator
presses the acknowledge button. A test button I is used to simulate a fire alarm for the
circuit testing .
(i) Draw the state diagram of the ﬁre alarm detector. [6 marks]
(ii) Obtain the NAND circuit equations of the ﬁre alarm detector. [9 marks] ~ In Figure Q7(b) Q8. A road intersection is controlled by a set of traffic lights. For each road the cycle of light
sequence is as follows: Road A: green yellow red red red red
Road B: red red red green yellow red Duration: 2min lOsec IDsec 2min lOsec lOsec The lights are driven by a timing signal X shown in Figure Q8 (i) Design the internal state diagram ofa suitable control system for the traffic lights of Road A and Road B with the timing sequence speciﬁed in Figure Q8.
[10 marks] (ii) Give the NAND circuit equations of the control system based on the internal state diagram
in (i).
[15 marks] (iii) Draw the circuit of the control system by using NAND gates.
[5 marks] Figure Q8(b) Q9(a)
The standard arrangement for displaying a decimal digit on a seven segment display as
shown in Figure Q9(a) «gwaaaeeogo Figure Q9(a)  (i) Derive the inputx‘output equations of a circuit (a decoder) that accepts the value of the
decimal digit and outputs a Il’on each terminal for which the corresponding segment is to be illustrated. Optimised the inputfoutput equations by using Kamaugh Maps.
[9 marks] (ii) Use the following PLA below to construct a BCDt07 segment decoder. The FLA outputs are to be activeLO W. (Note that the PAL only uses the Boolean equations without
simpliﬁcation for the BCDto7 segment decoder). [6 marks] (29(bl
Design a circuit to generate the two's complement of a given binary number as shown in
Figune(29(b)
(i) Tabulate the truth table of the two’s complement generator
' [6 niarks] (ii) Write the Boolean expressions of the two's complement generator. [6 marks]
(iii) Draw the circuit diagram of this circuit. [3 marks] (2")
a u
b v
C W
d x
e y
Jr 2 (35) Figure Q9(b) Q10(a).
Work out the Boolean expressions of
(i) a Module2 ’Down' Binaryr Counter, [3 marks]
(ii) a Module4 'Down’ Binary Counter and [3 marks]
(iii) a Modulo8 'Down' Binary Counter. [3 marks] (iv) Use the expressions above to deduce the Module2’1 FDownr Counter equations
by using JK ﬂipﬂops and NAND gates. [6 marks] Q10(b).
Design a Module—16 Gray code ’Up’ counter by using JK ﬂipﬂops and NAND gates.
(i) Draw the state diagram ofthe Gray Code Counter.
_ [5 marks]
(ii) Give the equations ofthe JK flipflops and the circuit of the Gray Code Counter.
[10 marks]
The sequence of the ModuloiG Gray Code is shown in Table Q10(b) Gray Codes ENumberiA Bjciog
50 3050:0]05
g1 iiio 0303‘
i2_ lilIOEOE
3 oligo 0i
‘4 13:11.0
1'5 11H 10 4'13 1i101 '14 1'001
15 0001I Table Q10(b) ...
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 Spring '07
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