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Unformatted text preview: CITY UNIVERSITY OF HONG KONG Course code & title : EE20200 Logic Circuit Design
Session : Semester A 19992000
Time allowed : 2 hours This paper has EIGHT pages. (Including this page). Module code & title : EE20200 Logic Circuit Design Instructions to candidates: 1. This paper contains TWO parts.
2. Students MUST answer all the questions in Part A. And choose TWO questions from
Part B. 3. Start a NEW page for EACH QUESTION. Materials, aids & instruments to be used during examination: Nonprogrammable portable battery operated calculator PART A (Answer all questions in this part  total of 40 marks) 1. A sequence 1010111 is received from a Hamming code system with even parity. Find the
transmitted information bits. Comment on the coding efficiency of the Hamming code system and states its limitation as an error detection and correction method.
[10 marks] 2. Simplify the following expression using Boolean Algebra. F(A,B,C,D)=ABCD+ZBC+ABED+A§E+ZBCB+AEC+ZBE+AEED [6 marks] 3. Use partitioning method to obtain a reduced stable table with minimum number of states
from the following state table. ' Hmommcnw>
>omm~nmomw [8 marks] 4. Figure below shows the configuration of a special circuit. Assume the initial condition of
QAQBQC are 000, ﬁnd the output condition of Z3, Z2, 21 and 20 for the ﬁrst 6 clock pulses. [8 marks] dOU‘WN‘O 5. Draw the timing diagram of the following circuit. Assuming that the initial conditions for
y1 y2 are “00” and both SET and CLR are tied to LOW. (Note: Submit your answer with Appendix.)
[8 marks] PART B (Choose two questions to answer  30 marks for each question) 6. Figure Q6 shows a simple railway track switching control for platforms A and B. Sensors
T, A and B give a logic HIGH signal if train is present. The switch gear status (SGS) signal
is set to HIGH if it is malfunction. The track is normally switched to platform A and its
corresponding switch gear control (SGC) signal is LOW, whilst the track will be switched
to platform B when SGC is set to HIGH. The control system is required to perform the
following tasks: i. An alarm signal (AS) will be given if the switch gear is malfunction or both
platforms A and B are occupied. ii. When there is an incoming train, a red signal (S) will be given if the switch gear is
malfunction or both platforms A and B are occupied. iii. The switch gear will switch the track to an unoccupied platform for the incoming
train to clock. (a) Tabulate the truth table of the operation of the control system. [6 marks]
(b) Use Kmap to obtain the simplified output logicvfunctions.  [6 marks] (c) Use two 4—to1 line MUXs and necessary logic gates to design the control system. [8 marks] (d) Use 3to8 line decoders and necessary logic gates to design the control system.
(Note: use T as the decoder enable input.) [10 marks] SGC
' swrtch gear
train control input senor A direction l El track A Platform A
Platform B sensor T red signal
5 sensor B track 3
switch gear
status
SGS Fi ure 6 Figure Q7 shows an circuit for performing arithmetic operations between two 4bit 2’s
complement number. The parallel 4bit adder is a ripple carry adder formed by four lbit
full—adders, with Cin, Z and Cout representing the carry in, sum and carry out, respectively. b) d) X Y M2 Complementer !
parallel 44262 binary adder ’ Parallel
' 4‘b't
Cour / 1 Figure Q7 An arithmetic circuit. Design a 1bit full—adder (FA) using NAND gates only. Assume that each NAND
gates has 20ns delay. Calculate the propagation delay of Carry and Sum. [8 marks] Use lbit FA blocks to construct a 4—bit binary ripple carry adder. Assuming that
each lbit FA block has the same properties as the one that you design in part a),
calculate the maximum propagation delay of the 4bit ripple carry adder. [6 marks] Use the minimum number of AND, OR and NOT gates to design the MUX circuit
shown in Figure Q7. (Note: the design should be based on a 2t01 M UX.) [5 marks] The One’s Complementer circuit in Figure Q7 performs the following function. Use minimum number of AND, OR and NOT gates to design the One’s
Complementer circuit. (Note: the design should be based on a single bit circuit.) [5 marks] Find the arithmetic operation (+, —) between X, Y and Z for all the combination of
MZMlMO. [6 marks] 8. A digital lock has two buttons X and Y. A HIGH signal will be generated when the button
is being pressed. An electromechanical interlock guaranteed that the two buttons cannot be
activated simultaneously. A control circuit with inputs X and Y, and an output Z has the
following features: i. A sequence of XX—YX will generate a HIGH signal Z to open the digital lock.
ii. An incorrect sequence will cause the digital lock to an error state. iii A new sequence detection begins when the digital lock is in the error state or when
the lock is opened. (a) Use Mealy machine, or otherwise, to draw the state diagram of the circuit. [8 marks]
(b) Obtain a reduced state table with minimum number of states using direct observation
method. , [6 marks] (c) Design and draw the circuit using I K ﬂipﬂops.
[12 marks] (d) Find the state equations of the circuit. _ [4 marks] APPENDIX Question 5: ...
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 Spring '07
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