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Unformatted text preview: CITY UNIVERSITY OF HONG KONG Course code & title : EEZOZOO‘Logic Circuit Design Session : Semester B 19992000 Time allowed : Two hours This paper has 7 pages. 1. This paper consists of 9 questions in 2 sections. 2. Answer ALL questions in Section A. And choose TWO questions from Section B.
3. Use a new page for each question. P1 Section A (48%)
Attempt ALL questions from this Section. Q1. Simplify the following expressions using boolean algebra: f(A,B, C, D) = Z m(1,3,4,9,11,12)
(6 marks) Q2. Use the PLA shown in Appendix to construct a logic circuit that multiplies twobit numbers, (am); and (b1b0)2. The product should be a fourbit number (p3p2p1po)2.
(Submit your answer with Appendix) (10 marks) Q3. (a) Brieﬂy explain the universal property of NAND gates.
(b) Redraw the following circuit shown in FigureQ3 using NAND gates only. FigureQ3
(8 marks) Q4. Use any method to obtain a reduced state table with minimum number of states from
the following state stable. next state/ou ut present state
A E/O A/l
B A/O
C E/O
D D/l
E D/O
F B/O
G B/ 1 (8 marks) P2 Q5. Q6. P3 Analyze the synchronous circuit of FigureQS. Find the state table and draw the state
diagram. FigureQS
(8 marks) Draw the timing diagram of the circuit shown in FigureQ6. Assume that the initial
condition for Q is low. (8 marks) Section B (52%)
Choose two question to answer26 marks for each question) Q7. (a) Design an even parity detector with the input and output shown in FigureQ7,
where a, b, c are the received ‘ data bits and p is the received parity bit. Draw your circuit.
a
output
input 11'
6 CP
p F igureQ7 Outut CP
— (7 marks) (b) Use the Hamming code (with even parity including the parity bit itself) to
encode the following 4bit message: 1001. ‘
(5 marks) (c) For the Hamming code used in part (b), decode the received bits 101 1110.
(6 marks) (d) Use a 3to8 decoder, the ﬁlnction blocks that you have designed in part(a),
and some extra gates to construct a logic circuit that decodes the Hamming code
used in part (b), where inputs are the received bits and outputs are the decoded
bits. Draw your circuit. (8 marks) P4 Q8. P5 (a) Brieﬂy discuss the similarity and difference between Mealy machines and
Moore Machines. (6 marks) (b) Use D ﬂipsﬂops to design a 3—bit synchronous gray code UP/DOWN counter.
The circuit has one control input x. When x =0, the circuit should operate as an
upcounter. Otherwise, it operates as downcounter. The following table
shows the decimal values of gray code numbers. Decimal vaues gray code (i) Find the state table of the gray code UP/DOWN counter.
(4 marks) (ii) Use D ﬂipﬂops and necessary gates to implement the gray code UP/DOWN
counter. Draw your circuit. (12 marks) (iii) Based on the results of (ii), suggest a simple way to implement the gray code
UP/DOWN counter by T ﬂipﬂops rather than D—ﬂip—ﬂops. (4 marks) Q9. P6 (a) The circuit, shown in FigureQ9(a), is a main component of a nbit serial
adder. Brieﬂy describe how to use it to perform the nbit addition operation. asynchronous reset Figure Q9(a) (6 marks) (b) Use 4to1 MUXs and necessary gates to implement a 3bit logic unit which performs four logic operations on two 3bit binary numbers, A = (a2,a1,a0) and B = (b2,b1,b0) , given by the following table.
(Hint: desi a one—bit lo ic unit ﬁrst function output result
ﬂ —nnm
Dun—
—II_
_m (6 marks) (c) Use lbit ﬁill adder modules and necessary gates to construct a 3bit carry
lookahead full adder. Draw your circuit. (1 0 marks) (d) Use the results of part (b) and part (c) to construct a 3bit arithmetic and
logic unit, which performs some arithmetic or logical operation on two 3bit binary numbers, A = (a2,a1,a0) and B = (b2,b1,b0) . The 3bit result
and carry output are denoted as F = (f2,f1, f0) and c0“, , respectively. (4 marks)
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 Spring '07
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