Lecture4-Gates_Design_Rules-6up

Lecture4-Gates_Design_Rules-6up - EE141-Fall 2010 Digital...

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EE141 1 EECS141 1 Lecture #4 EE141 EE141 -Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 4 Lecture 4 CMOS Switches and Gates CMOS Switches and Gates Design Rules Design Rules EE141 2 EECS141 2 Lecture #4 Administrative Stuff Administrative Stuff ± For this week, Hanh-Phuc’s office hours moved to today, 4-5pm (481 Cory) ± Labs start this week ² Software lab #2 starts Friday ² Lab reports due the following week in lab ± Homework #2 due this Thurs. ² Homework #3 out this Thurs. EE141 3 EECS141 3 Lecture #4 Review: Review: VTCs EE141 4 EECS141 4 Lecture #4 Review: Delay Review: Delay ± Is it possible for a gate to have negative delay? EE141 5 EECS141 5 Lecture #4 Review: Energy Review: Energy ± Pulsed inverter EE141 6 EECS141 6 Lecture #4 Class Material ± Last lecture ² Transistor as a switch, inverter ² Design metrics ± Today’s lecture ² Detailed switch model ² CMOS gates (intro to Ch. 3, 6) ² Design rules (Ch. 2.3) ± Reading (2.3, 3.3.1-3.3.2, 6.1-6.2.1)
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EE141 7 EECS141 7 Lecture #4 Switch Model of MOS Transistor | V GS | SD G |V GS | < | V T || V GS | > | V T | R on EE141 8 EECS141 8 Lecture #4 MOS Switch Model (Capacitance) MOS Switch Model (Capacitance) EE141 9 EECS141 9 Lecture #4 Switch Model (Width) EE141 10 EECS141 10 Lecture #4 CMOS Inverter Model CMOS Inverter Model V in V out C L V DD EE141 11 EECS141 11 Lecture #4 CMOS Logic CMOS Logic EE141 12 EECS141 12 Lecture #4 The CMOS Inverter: A First Glance V in V out C L V DD
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EE141 13 EECS141 13 Lecture #4 Static CMOS Gates At every point in time (except during the switching transients) each gate output is connected to either V DD or V SS via a low resistive path.
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Fall '08 term at University of California, Berkeley.

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Lecture4-Gates_Design_Rules-6up - EE141-Fall 2010 Digital...

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