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Lecture4-Gates_Design_Rules-6up

Lecture4-Gates_Design_Rules-6up - EE141-Fall 2010 Digital...

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EE141 1 EECS141 1 Lecture #4 EE141 EE141- Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 4 Lecture 4 CMOS Switches and Gates CMOS Switches and Gates Design Rules Design Rules EE141 2 EECS141 2 Lecture #4 Administrative Stuff Administrative Stuff For this week, Hanh-Phuc’s office hours moved to today, 4-5pm (481 Cory) Labs start this week Software lab #2 starts Friday Lab reports due the following week in lab Homework #2 due this Thurs. Homework #3 out this Thurs. EE141 3 EECS141 3 Lecture #4 Review: Review: VTCs EE141 4 EECS141 4 Lecture #4 Review: Delay Review: Delay Is it possible for a gate to have negative delay? EE141 5 EECS141 5 Lecture #4 Review: Energy Review: Energy Pulsed inverter EE141 6 EECS141 6 Lecture #4 Class Material Last lecture Transistor as a switch, inverter Design metrics Today’s lecture Detailed switch model CMOS gates (intro to Ch. 3, 6) Design rules (Ch. 2.3) Reading (2.3, 3.3.1-3.3.2, 6.1-6.2.1)
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