Lecture7-LE-6up - EE141-Fall 2010 Digital Integrated...

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EE141 1 EECS141 1 Lecture #7 EE141 EE141 -Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 7 Lecture 7 Gate Delay and Gate Delay and Logical Effort Logical Effort EE141 2 EECS141 2 Lecture #7 Announcements Announcements ± Lab #3 this Fri., next Mon. ± Homework #3 due today ² Homework #4 due next Thursday EE141 3 EECS141 3 Lecture #7 Class Material Class Material ± Last lecture ² Inverter delay optimization ± Today’s lecture ² Gate delay and logical effort ± Reading (Chapter 6) EE141 4 EECS141 4 Lecture #7 Complex Gate Delay Complex Gate Delay ± Use RC model to estimate delay: C L B R n A R p B R p A R n C int EE141 5 EECS141 5 Lecture #7 Complex Gate Delay (2) Complex Gate Delay (2) ± Now what is the delay? C L B R n A R p B R p A R n C int EE141 6 EECS141 6 Lecture #7 Elmore Delay Elmore Delay • “Elmore delay”: approximation for delay of arbitrary (complex) RC circuits • To find “Elmore time constant”: • For each capacitor, draw path of current from cap to input • Multiply C by sum of R’s on current path that are common with path from V in to V out • Add up RC products from all capacitors
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EE141 7 EECS141 7 Lecture #7 Elmore Delay (Formal Method) Elmore Delay (Formal Method) •Se t±V in to (incremental) ground • Apply current I across C, measure V out • Calculate R eff = V out / I Time constant due to that C is R eff *C EE141 8 EECS141 8 Lecture #7 Simplified Model: Elmore Delay Simplified Model: Elmore Delay () ( ) 11 1 2 2 1 2 3 3 Elmore R CRR CRRR C τ =+ + + + + EE141 9 EECS141 9 Lecture #7 Another Elmore Delay Example Another Elmore Delay Example R 1 C 1 R 2 C 2 V out V in R 3 C 3 Elmore = EE141 10 EECS141 10 Lecture #7 Another Example Gate Another Example Gate EE141 11
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Lecture7-LE-6up - EE141-Fall 2010 Digital Integrated...

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