Lecture8-Decoder_LE-6up - EE141-Fall 2010 Digital...

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EE141 1 EECS141 1 Lecture #8 EE141 EE141 -Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 8 Lecture 8 LE for Decoders LE for Decoders EE141 2 EECS141 2 Lecture #8 Announcements Announcements ± Lab #3 Mon., Lab #4 Fri. ± Homework #4 due this Thursday ² Homework #5 due next Thursday EE141 3 EECS141 3 Lecture #8 Class Material Class Material ± Last lecture ² Gate delay and logical effort ± Today’s lecture ² Logical effort for decoders ± Reading (Chapter 6) EE141 4 EECS141 4 Lecture #8 Decoders Decoders EE141 5 EECS141 5 Lecture #8 Decoder Design Example Decoder Design Example ± Look at decoder for 256x256 memory block (8KBytes) EE141 6 EECS141 6 Lecture #8 Problem Setup ± Goal: Build fastest possible decoder with static CMOS logic ± What we know ² Basically need 256 AND gates, each one of them drives one word line N=8
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EE141 7 EECS141 7 Lecture #8 Problem Setup (1) Problem Setup (1) ± Each word line has 256 cells connected to it ± C WL = 256*C cell + C wire ² Ignore wire for now (include it later in the class) EE141 8 EECS141 8
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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Lecture8-Decoder_LE-6up - EE141-Fall 2010 Digital...

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