Lecture12-Delay_Power-6up

Lecture12-Delay_Power-6up - EE141-Fall 2010 Digital...

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EE141 1 EECS141 1 Lecture #12 EE141 EE141 -Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 12 Lecture 12 CMOS Delay and CMOS Delay and Power Models Power Models EE141 2 EECS141 2 Lecture #12 Announcements ± Lab #5 this Fri., next Mon. ± Midterm #1 Thurs., 6:30-8:00pm ² Be sure to arrive on time ± Homework #6 out this Thurs., due next Thurs. EE141 3 EECS141 3 Lecture #12 Class Material Class Material ± Last lecture ² MOS Capacitance, delay ± Today’s lecture ² Improved CMOS Delay and Power Models ± Reading (5.1-5.3, 5.4.2) EE141 4 EECS141 4 Lecture #12 Propagation Delay Propagation Delay EE141 5 EECS141 5 Lecture #12 0 0.5 1 1.5 2 2.5 x 10 -10 -0.5 0 0.5 1 1.5 2 2.5 3 t (sec) V out (V) Transient Response Transient Response t pHL = ln(2) C L R eqn t pLH = ln(2) C L R eqp t pHL t pLH () 11 2ln(2) 1 = + DD eq DD DSAT V R λ VI EE141 6 EECS141 6 Lecture #12 Step Inputs? Step Inputs? ± Derived RC model assuming input was a step ² But input is not a step ² Transistor turns on gradually ± Let’s look at gate switching more carefully ² Use our models to understand the effect of input slope
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EE141 7 EECS141 7 Lecture #12 Input Slope Dependence Input Slope Dependence ± One way to analyze slope effect ² Plug non-linear IV into diff. equation and solve… ± Simpler, approximate solution: ² Use V T * model out out L NMOS PMOS dV IC I I dt == EE141 8 EECS141 8 Lecture #12 Slope Analysis Slope Analysis ± For falling edge at output: ² For reasonable inputs, can ignore I PMOS ² Either V ds is very small, or V gs is very small ± So, output current ramp starts when V in = V T * ² Could evaluate the integral implied by slide 7 ² Learn more by using an intuitive, graphical approach EE141 9 EECS141 9 Lecture #12
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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Lecture12-Delay_Power-6up - EE141-Fall 2010 Digital...

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