Lecture13-CMOS_Logic-6up - EE141-Fall 2010 Digital...

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EE141 1 EECS141 1 Lecture #13 EE141 EE141 -Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 13 Lecture 13 CMOS Logic Review CMOS Logic Review EE141 2 EECS141 2 Lecture #13 Announcements Announcements ± Lab #5 tomorrow, next Mon. ± Homework #6 out today, due next Thurs. ± Reminder: ² Project coming up in 2 weeks – find a partner EE141 3 EECS141 3 Lecture #13 Class Material Class Material ± Last lecture ² CMOS Delay and Power Models ± Today’s lecture ² CMOS Logic Review ± Reading (6) EE141 4 EECS141 4 Lecture #13 CMOS Logic Review Review EE141 5 EECS141 5 Lecture #13 Cell Design Cell Design ± Standard Cells ² General purpose logic ² Used to synthesize RTL/HDL ² Same height, varying width ± Datapath Cells ² For regular, structured designs (arithmetic) ² Includes some wiring in the cell EE141 6 EECS141 6 Lecture #13 Standard Cell Layout Methodology Standard Cell Layout Methodology 1980s 1980s signals Routing channel V DD GND
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EE141 7 EECS141 7 Lecture #13 Standard Cell Layout Methodology Standard Cell Layout Methodology 1990s 1990s - Today Today M2 No routing channels V DD GND M3 V DD GND Mirrored Cell Mirrored Cell EE141 8 EECS141 8
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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Lecture13-CMOS_Logic-6up - EE141-Fall 2010 Digital...

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