Lecture18-Ratio_PTL-6up - EE141-Fall 2010 Digital...

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EE141 1 EECS141 1 Lecture #18 EE141 EE141 -Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 18 Lecture 18 Ratioed Ratioed and Pass and Pass Transistor Logic Transistor Logic EE141 2 EECS141 2 Lecture #18 Announcements Announcements ± Project #1 due Thursday ± Midterm 2: Thurs. Nov. 4 th , 6:30- 8:00pm, Location TBD ² Review session time/day TBA EE141 3 EECS141 3 Lecture #18 Ratioed Ratioed Logic Logic EE141 4 EECS141 4 Lecture #18 Ratioed Ratioed Logic Logic V DD V SS PDN In 1 In2 In 3 F R L Load V DD V SS In 1 In2 In 3 F V DD V SS PDN In 1 In2 In 3 F VSS PDN Resistive Depletion Load PMOS Load (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS VT < 0 Goal: build gates faster/smaller than static complementary CMOS EE141 5 EECS141 5 Lecture #18 Ratioed Logic Ratioed Logic ± Spend power for speed ² Use pseudo nMOS NOR gates, not NAND gates ± DC characteristics: ² V OH = V DD ² V OL depends on PMOS to NMOS ratio W W W W EE141 6 EECS141 6 Lecture #18 Pseudo -NMOS VTC NMOS VTC 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V in [V] V ou t [V] W/L p = 4 W/L p = 2 W/L p = 1 W/L p = 0.25 W/L p = 0.5
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EE141 7 EECS141 7 Lecture #18 Ratioed Logic LE Ratioed Logic LE ± Rising and falling delays aren’t the same ² Calculate LE for the two edges separately ± For tpLH: ² C gate = WC G C inv = (3/2)WC G LE LH = EE141 8 EECS141 8 Lecture #18 Ratioed Logic LE (pull
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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Lecture18-Ratio_PTL-6up - EE141-Fall 2010 Digital...

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