Lecture23-Flops_Latches-6up

Lecture23-Flops_Latches-6up - EE141-Fall 2010 Digital...

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EE141 1 EECS141 1 Lecture #23 EE141 EE141 -Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 23 Lecture 23 Flops and Latches Flops and Latches EE141 2 EECS141 2 Lecture #23 Announcements Announcements ± Homework #8 due next Tuesday ± Project Phase 3 plan due this Sat. EE141 3 EECS141 3 Lecture #23 Sequential Elements: Sequential Elements: Flops and Latches Flops and Latches EE141 4 EECS141 4 Lecture #23 Why Sequencing? Why Sequencing? EE141 5 EECS141 5 Lecture #23 Sequential Elements Sequential Elements ± Latch – level sensitive ² Clk=0: “opaque” ² Clk-1: “transparent” ± Flip-flop – edge triggered ² Stores new data when Clk rises D Clk Q D Clk Q Clk Clk D D QQ EE141 6 EECS141 6 Lecture #23 Timing Definitions - REVIEW REVIEW t CLK t D t c ¹ q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ
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EE141 7 EECS141 7 Lecture #23 Storage Mechanisms Storage Mechanisms D CLK CLK Q Static Latch D CLK CLK Q Dynamic Latch EE141 8 EECS141 8 Lecture #23 Writing Into a Static Latch Writing Into a Static Latch CLK CLK CLK D Q D CLK CLK Q Converting into a MUX (gated feedback) Forcing the state EE141 9 EECS141 9 Lecture #23 Master Master -Slave Flip Slave Flip -Flop (Edge Flop (Edge - Triggered Register) Triggered Register) 1 0 D CLK Q M Master 0 1 CLK Q
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Lecture23-Flops_Latches-6up - EE141-Fall 2010 Digital...

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